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In my experience the step of leaving von Neumann architecture and programming that data flows across the compute engines is the more difficult step than the cra
by jeffreygoesto 2y ago
In my experience the step of leaving von Neumann architecture and programming that data flows across the compute engines is the more difficult step than the crappy FPGA tools. I tell people that with an FPGA you teach the computer what to be, not what to do. A bit like functional vs. imperative programming.
Therefore I can't yet imagine how to easier onboard people who learned on a "classical CPU". Can you go a bit deeper in what makes your system easier to program?
- mikewarot 2y agoFPGAs are heterogeneous, and the tools are all about getting the maximum utilization of a given chip's features while also routing signals to get the fastest reliable cycle times. Compile times sometimes stretch out into overnight sessions. By making each cell identical you remove most of the floor planning concerns. By latching the data from each cell, you remove timing concerns, and deliver deterministic performance. This has other benefits like being possible to route around a bad cell, or to build a "wall" around a given section of code. The emulator will always give correct output baring hardware failure. I hope to get through tiny Tapeout and have a chip before the end of the year. As for programming, the code has to compile to a directed acyclic graph of boolean logical operations. I suspect that it would be fairly easy to use as a backend for tinygrad or perhaps LLVM as a stretch goal.
- jeffreygoesto 2y agoAh thanks! Reminds me of systolic arrays somehow. Good luck and hopefully there are no bugs in your design!