If you're simulating a complex CPU's HDL in Verilator then think in terms of single digit thousands of instructions per second. Vs single digit billions of inst

If you're simulating a complex CPU's HDL in Verilator then think in terms of single digit thousands of instructions per second. Vs single digit billions of instructions per second when it's made into an SoC. i.e. on the order of a million times slower than the final product. On an FPGA you might get 20 to 50 million instructions per second, only 100 times slower than the final SoC product. But for a large modern OoO design you'll need an FPGA costing $15000 (for a VCU118) or even more.