4 ms·
It's possible to get gcc to generate sequences that would trigger this: https://godbolt.org/z/rYKqPxn7b https://godbolt.org/z/rYKqPxn7b
by tavianator 2y ago
It's possible to get gcc to generate sequences that would trigger this: https://godbolt.org/z/rYKqPxn7b https://godbolt.org/z/rYKqPxn7b
- loeg 2y agoThe godbolt paste I'm looking at shows GCC generating a SAL with 8 bit shift (CL), not a SHLX with 64-bit shift (RCX).
- tjalfi 2y agoGCC will generate the shlx instruction if you add the -mbmi2 flag to your build options. For example, you can see this in action here: https://godbolt.org/z/asb1fxos5 https://godbolt.org/z/asb1fxos5.
- BeeOnRope 2y agoIt's true, I was considering only the original mov rax, 1 case, which I'm pretty sure compilers don't generate: it's just a useless encoding of mov eax, 1. Given that 64-bit immediate math also causes this though, compilers might generate it (I think this is a minor missed optimization by gcc though: it could have used add eax, 1 instead.
- deleted 2y ago[deleted]
- tavianator 2y agoSHL suffers from the same latency issue as SHLX it turns out
- loeg 2y agoSAL as well? (And anyway this example seems to be shifting by the low 8 bits of RCX (CL), not the full width register.)
- tavianator 2y agoSAL and SHL are synonyms, they have the same encoding. SHL only accepts CL as the count register, there's no other form that takes a variable shift count
- loeg 2y agoAhh, thanks, I didn't make that connection.
- Bulat_Ziganshin 2y agoIntel shifts anyway mask out higher bits of CL, this hurts sometimes e.g. when you need to shift by 1..64 bits