3 ms·

https://github.com/OpenXiangShan/XiangShan-doc/blob/main/docs/frontend/decode.md https://github.com/OpenXiangShan/XiangShan-doc/blob/main/doc... The list of fu

https://github.com/OpenXiangShan/XiangShan-doc/blob/main/docs/frontend/decode.md https://github.com/OpenXiangShan/XiangShan-doc/blob/main/doc... The list of fused instructions is kinda weird; besides the ones that correspond to SH{1,2,3,4}ADD anyway, I don't think I expected any of the others. I don't see a mention of Sifive-style short jump predication there either, though I'm using Google Translate.

deleted 2y ago
[deleted]
zozbot234 2y ago
Does RISC-V org itself list/document suggested insn fusion sequences anywhere? I can't quite figure out whether they do because the technical wiki they use is quite hard to navigate and search, and their unofficial Github repos are not much better.
- snvzz 2y ago
  You might find this[0] reddit thread useful. 0. https://old.reddit.com/r/RISCV/comments/1hnm5y1/where_did_the_pseudo_instructions_list_go/ https://old.reddit.com/r/RISCV/comments/1hnm5y1/where_did_th...
  - zozbot234 2y ago
    That's talking about the list of pseudo-instructions, which are just special-cased assembly mnemonics for a single RISC insn. I'm wondering whether there's also a documented list of suggested fusable sequences, comprising multiple insns each.
    - snvzz 2y ago
      You'll find that a lot of them are equivalent to a sequence of -i.e. more than one- instructions. Refer to the "base instruction" column in the pseudoinstruction table[0]. 0. https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/src/asm-manual.adoc#a-listing-of-standard-risc-v-pseudoinstructions https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/...
- Arnavion 2y ago
  The ISA spec itself suggests one fusion - that of mul and mulh (lower and upper halves of n-bit * n-bit -> 2n-bit product). The only other source I know of was this 2016 paper that suggested specific macro fusions. https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318 This predates the B extension so some of those fusions are dedicated instructions now, but I suppose Xiangshan still implements them for the sake of software that was not compiled with B enabled.

deleted 2y ago

[deleted]

zozbot234 2y ago

Does RISC-V org itself list/document suggested insn fusion sequences anywhere? I can't quite figure out whether they do because the technical wiki they use is quite hard to navigate and search, and their unofficial Github repos are not much better.

snvzz 2y ago
You might find this[0] reddit thread useful. 0. https://old.reddit.com/r/RISCV/comments/1hnm5y1/where_did_the_pseudo_instructions_list_go/ https://old.reddit.com/r/RISCV/comments/1hnm5y1/where_did_th...
- zozbot234 2y ago
  That's talking about the list of pseudo-instructions, which are just special-cased assembly mnemonics for a single RISC insn. I'm wondering whether there's also a documented list of suggested fusable sequences, comprising multiple insns each.
  - snvzz 2y ago
    You'll find that a lot of them are equivalent to a sequence of -i.e. more than one- instructions. Refer to the "base instruction" column in the pseudoinstruction table[0]. 0. https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/src/asm-manual.adoc#a-listing-of-standard-risc-v-pseudoinstructions https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/...
Arnavion 2y ago
The ISA spec itself suggests one fusion - that of mul and mulh (lower and upper halves of n-bit * n-bit -> 2n-bit product). The only other source I know of was this 2016 paper that suggested specific macro fusions. https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318 This predates the B extension so some of those fusions are dedicated instructions now, but I suppose Xiangshan still implements them for the sake of software that was not compiled with B enabled.