4 ms·
Woah that's weird. Left shifting either takes 3 cycles or 1 cycle, depending on how you initialize the cycle count register? This patch from the article makes
by aftbit 2y ago
Woah that's weird. Left shifting either takes 3 cycles or 1 cycle, depending on how you initialize the cycle count register?
This patch from the article makes it take 1 cycle instead of 3:
- MOV RCX, 1
+ MOV ECX, 1
>It seems like SHLX performs differently depending on how the shift count register is initialized. If you use a 64-bit instruction with an immediate, performance is slow. This is also true for instructions like INC (which is similar to ADD with a 1 immediate).
Practically speaking, is this sort of µop-dependent optimization implemented by compilers? How do they do so?
- tavianator 2y ago> Practically speaking, is this sort of µop-dependent optimization implemented by compilers? I suspect this specific thing is not; I don't think many people were aware of this anomaly until this week. I doubt the compilers are modeling it. But in general, compilers will have a machine model that predicts the cost of different instructions. The backend will try to generate instruction sequences with low cost, so if you include this anomaly in the model it will probably work around it automatically. This old example might interest you: a false dependency on the destination register for `popcnt` on some uarches led to compiler patches: https://stackoverflow.com/q/25078285/502399 https://stackoverflow.com/q/25078285/502399
- RossBencina 2y agouser mshockwave posted this the other day in a comment, might be of interest/tangential relevance: Scheduling Model in LLVM - Part I https://myhsu.xyz/llvm-sched-model-1 https://myhsu.xyz/llvm-sched-model-1
- loeg 2y agohttps://news.ycombinator.com/item?id=42555110 https://news.ycombinator.com/item?id=42555110