3 ms·
Plus Apple themselves are already kind of doing it with the M Ultras - those are two chiplets glued together, each of which is only connected to half of the sys
by jsheard 2y ago
Plus Apple themselves are already kind of doing it with the M Ultras - those are two chiplets glued together, each of which is only connected to half of the systems memory directly, but it still behaves like unified memory even though half of the memory traffic has to be routed via the other chiplet.
- wtallis 2y agoAnd in the datacenter space, AMD has taken things even further with the MI300A: > Twenty-four x86-architecture ‘Zen 4’ cores in three chiplets > Six accelerated compute dies (XCDs) with 38 compute units (CUs), each with 32 KB of L1 cache, 4 MB L2 cache shared across CUs, and 256 MB AMD Infinity Cache™ shared between XCDs and CPUs > 128 GB of HBM3 memory shared coherently between CPUs and GPUs with 5.3 TB/s on-package peak throughput
- sliken 2y agoIndeed. Very similar to the grace + hopper, grace + dual hopper, and grace + dual blackwell.