4 ms·
So many different cores. Dual M33s, VPR, consisting of PPR (a low power 16 MHz RISC-V RV32E? for external I/O) and FLPR (a RISC-V RV32E running at 320 MHz, for
by vardump 2y ago
So many different cores.
Dual M33s, VPR, consisting of PPR (a low power 16 MHz RISC-V RV32E? for external I/O) and FLPR (a RISC-V RV32E running at 320 MHz, for software defined peripherals).
I wonder what the max square wave GPIO toggle rate is with FLPR. Can it compete with for example RP2040/2350 PIO?
- crest 2y agoThey would have to fuck up massively for an I/O co-processor to lack single cycle GPIO access which would at least allow driving a 320/2 50% duty-cycle square wave, but sustaining that deterministically through priority access to memory and DMA is something else. At 150MHz the RP2350 is able to sustain that bandwidth with hard realtime guarantees allowing it to do things which are hard to impossible on other chips in the same price class e.g. glitchfree 720p video output "in software".
- petra 2y agoI wonder if that will be the effect of the rp2350, to push the whole market toward software defined peripherals?
- MisterTea 2y agoI would say not really as software defined peripherals have been around for some time. There is the Parallax Propeller and Greenarrays chips which have no hard IO blocks, everything is done in CPU cores. The Ti PRU is similar.