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No love for a verilog design in an fpga as open source hardware? It’s a flawed surrogate of course - lower performance and higher cost than an asic produced at
by beng-nl 2y ago
No love for a verilog design in an fpga as open source hardware?
It’s a flawed surrogate of course - lower performance and higher cost than an asic produced at volume - but the open source hardware aspect is very strong.
- fecal_henge 2y agoThe circuitry (ie transistor level) of the FPGA is still closed no?
- rbanffy 2y agoIt's not open unless you can make it from sand. Actually, it's not open unless you can make it from hydrogen atoms.
- teddyh 2y agoThat’s going too far. RYF certification is what you could reasonably require.
- beng-nl 2y agoYes, but there are many different fpga’s, many of which many verilog will run on, which to my mind makes the downsides of proprietyness low enough that this might be the sweet spot to stop at going down the stack.. however awesome an open source fabbed asic or fpga would be of course.