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It's interesting that there's no "trap instruction/sequence" feature built into the CPU architecture. That would presumably be valuable for auditing and debugg
by hakfoo 2y ago
It's interesting that there's no "trap instruction/sequence" feature built into the CPU architecture. That would presumably be valuable for auditing and debugging, or to create a custom instruction by trapping an otherwise unused bit sequence.
- j16sdiz 2y ago> create a custom instruction by trapping an otherwise unused bit sequence. .. ... until a new CPU support an instruction extension that use the same bit sequence.
- immibis 2y agoThat's why architectures - including x86! - have opcodes they promise will always be undefined.
- colejohnson66 2y agoThose undefined opcodes are more for testing your fault handler or for forcing a trap in an “unreachable” part of your code, not to implement custom instructions.
- phire 2y agoYeah... Part of the reason why existing functionality is limited and nobody uses them to implement custom instructions, is that trapping is actually quite expensive. The switch to kernel space and back is super expensive, but even if a CPU did implemente fast userspace trap handlers, it wouldn't be fast.
- immibis 2y agoThey can be used for anything you want. The CPU treats them as described in the document. They're not fast, though. You probably don't want to run trapped fake instructions in tight loops, but you don't want that no matter how they're implemented.
- Tuna-Fish 2y agoThere is today, for all the reasons you state. Transistor budgets were tighter back then.