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The cache behavior regarding the ordering of memory accesses cannot be configured. What you can select when mapping memory is to make some regions uncached (wi
by adrian_b 2y ago
The cache behavior regarding the ordering of memory accesses cannot be configured.
What you can select when mapping memory is to make some regions uncached (with several variants, e.g. write-combining).
Some of the kinds of uncached memory regions, especially those whose names include "write-combining", implement weaker orderings of the memory accesses in comparison with how cacheable memory works on x86, where 3 of the 4 kinds of memory access reorderings are prohibited (i.e. all except that subsequent loads can be performed before prior stores).
However choosing a memory type with weakly-ordered accesses cannot increase the performance on x86, because the loss of performance by not using the cache is much greater.
The weakly-ordered accesses only recover a small part of the performance loss caused by uncached memory.
- jcranmer 2y agoIs the mapping memory stuff separate from what's being set up by the OS as part of the TLB? I'm generally willfully ignorant of the privileged side of ISAs since I'm firmly a compilers guy, so I mostly only got this level of stuff by having to look at it thanks to it being incorporated into the definition of nontemporal store on x86 (which still ends up being confusing as heck).
- NobodyNada 2y agoYes, the "mapping memory stuff" is the page tables. (The TLB is an internal cache the processor keeps of recently used page table entries, which is mostly internal to the processor and transparent to the OS, except that the OS needs to remember to issue a special instruction to invalidate the TLB after modifying page tables.)