3 ms·
it takes time (~2 years) for silicon designers to go from idea to taping out silicon. The P550's cores are advertised as having good area efficiency, so it coul
by 6SixTy 2y ago
it takes time (~2 years) for silicon designers to go from idea to taping out silicon. The P550's cores are advertised as having good area efficiency, so it could be both getting rid of the vector extensions to optimize area and they just couldn't incorporate them into the design.
I is the base integer instructions
M is integer multiplication
A is atomic
F is single precision float
D is double precision
G is shorthand for all of the above + 2 others that I honestly have no idea what they do
- mshockwave 2y ago> 2 others that I honestly have no idea what they do CSR (i.e. status) register and instruction fence extensions. Instruction fences are most useful in cases where you modify text section during runtime (e.g. JIT or code hot reload) such that you need to ensure the consistency of code across different harts
- jecel 2y ago> + 2 others that I honestly have no idea what they do The original RV32I and RV64I required some control registers for high frequency counters and instruction counters. You also needed the instructions to access these registers. This proved to be too complex for the simplest implementations, so recently (five years ago?) this functionality has been moved to their own extensions. Including these extensions in G makes the current G have the same functionality as the original G.
- snvzz 2y agoImportant to highlight this happened before the base RISC-V specs were ratified. i.e. features have not been removed after ratification.
- cmrdporcupine 2y agoOk, wow I didn't even clue in that the IMAFD was other extensions, and the G a "rollup" of them, because last time I played with RISC-V it was just with cores that did IMF