4 ms·

Can someone who is more familiar with this SoC confirm for me that this P550 doesn't have the RISC-V "V" vector extensions? I'm seeing a GBC suffix which I gues

Can someone who is more familiar with this SoC confirm for me that this P550 doesn't have the RISC-V "V" vector extensions? I'm seeing a GBC suffix which I guess means bit manipulation, compressed instructions, and whatever the G extension is which I don't fully understand (IMAFD plz explain?)

insom 2y ago
G includes MAFD extensions for non-embedded (I) applications. That's multiplication and division, atomics, single and double-precision floating point. It also includes the control/status register and a instruction-fence instruction. I think it's there to mean "the base plus the standard bits that people generally want in a processor if they're writing C for it".
- cmrdporcupine 2y ago
  Ah, ok, thanks for the clarification. When I last played with RISC-V it was in (hobby) FPGA stuff and the cores I was messing with did not specify G.
lauriewired 2y ago
P550 cores don't have vector extensions. It's actually quite an old design, from 2021. What you'd want is SiFive P670 cores, which are RVA22 compliant with the vector 1.0 spec.
- brucehoult 2y ago
  Three years from announcement of a core to SoCs on boards being available is actually on the quick side. Arm A53 (Pi 3, October 2012 - February 2016), A72 (Pi 4, Feb 2015 - June 2019), and A76 (Pi 5, May 2018 - September 2023, or January 2022 for Radxa Rock 5B) all took longer. P670 was only announced in November 2022. If a board ships by the end of 2025 it will be doing very well.
  - adgjlsfhk1 2y ago
    why does it take so long? I totally understand for leading edge products on new nodes why it would, but for chips on mature processes, what's the bottleneck between design and sale? I know the round trip time from the foundries is ~3 months. Is the rest validation? It feels like it would be really valuable to be able to reduce the time to ~1 year (even if that came at the cost of power, area or a moderate amount of performance). Shortening the feedback loop here would be super helpful for designers and programmers to be able to experiment with new paradigms faster I would think.
    - brucehoult 2y ago
      Largely because in the Arm and RISC-V worlds company A designs the CPU core, then at some point company B decides to license the core to make an SoC and starts designing it. Then company C manufactures the chip. Then when the chip is available companies D, E, F design boards for the chip to go on. Traditionally in x86 Intel and AMD do all the first three steps in one company, with the stages overlapped, and feedback. Also, Intel and AMD (and even more so Apple) don't announce a new chip until it is very close to shipping. They might have been working on it internally for five years before that. Arm and RISC-V companies have to make public announcements when a core is nearing design completion, to give a chance for companies such as Allwinner and Rockchip and Broadcom and Mediatek and Sophgo and Starfive to take a look at the specs and decide that it might be interesting to build a chip using that core. > I know the round trip time from the foundries is ~3 months. That's only if the chip works first time. Many don't and need several re-spins. I believe 3 or 4 is not uncommon. And variable amounts of re-design and re-layout and re-verify time between each of those ~3 months at the foundry. Given that, it would be a brave company that went straight to mass-production without a round of test chips first, so you've got 2x ~3 months, plus "bring up" time in between, even in the best case.
aseipp 2y ago
The only board that is cheap and available with the ratified 1.0 vector extension I know of is the Kendryte K230, which you can find on some boards for about $40 USD: https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html https://developer.canaan-creative.com/k230/dev/zh/00_hardwar... Note that it's only on one 1.6GHz core, and still pretty anemic otherwise (pi form factor, it's to be expected.) So something "deskop grade" with all the nice extensions and other goodies is probably still a ways off. Maybe next year; we'll have to see -- but lots of useful extensions continue to be ratified today, so it may still be a while before things "cool off."
- mshockwave 2y ago
  SpacemiT K1 on BananaPi is another commonly seen RVV 1.0 capable chip. IIRC both Kendryte K230 and SpacemiT K1 are in-order cores.
6SixTy 2y ago
it takes time (~2 years) for silicon designers to go from idea to taping out silicon. The P550's cores are advertised as having good area efficiency, so it could be both getting rid of the vector extensions to optimize area and they just couldn't incorporate them into the design. I is the base integer instructions M is integer multiplication A is atomic F is single precision float D is double precision G is shorthand for all of the above + 2 others that I honestly have no idea what they do
- mshockwave 2y ago
  > 2 others that I honestly have no idea what they do CSR (i.e. status) register and instruction fence extensions. Instruction fences are most useful in cases where you modify text section during runtime (e.g. JIT or code hot reload) such that you need to ensure the consistency of code across different harts
- jecel 2y ago
  > + 2 others that I honestly have no idea what they do The original RV32I and RV64I required some control registers for high frequency counters and instruction counters. You also needed the instructions to access these registers. This proved to be too complex for the simplest implementations, so recently (five years ago?) this functionality has been moved to their own extensions. Including these extensions in G makes the current G have the same functionality as the original G.
  - snvzz 2y ago
    Important to highlight this happened before the base RISC-V specs were ratified. i.e. features have not been removed after ratification.
- cmrdporcupine 2y ago
  Ok, wow I didn't even clue in that the IMAFD was other extensions, and the G a "rollup" of them, because last time I played with RISC-V it was just with cores that did IMF

insom 2y ago

G includes MAFD extensions for non-embedded (I) applications. That's multiplication and division, atomics, single and double-precision floating point. It also includes the control/status register and a instruction-fence instruction. I think it's there to mean "the base plus the standard bits that people generally want in a processor if they're writing C for it".

cmrdporcupine 2y ago
Ah, ok, thanks for the clarification. When I last played with RISC-V it was in (hobby) FPGA stuff and the cores I was messing with did not specify G.

lauriewired 2y ago

P550 cores don't have vector extensions. It's actually quite an old design, from 2021. What you'd want is SiFive P670 cores, which are RVA22 compliant with the vector 1.0 spec.

brucehoult 2y ago
Three years from announcement of a core to SoCs on boards being available is actually on the quick side. Arm A53 (Pi 3, October 2012 - February 2016), A72 (Pi 4, Feb 2015 - June 2019), and A76 (Pi 5, May 2018 - September 2023, or January 2022 for Radxa Rock 5B) all took longer. P670 was only announced in November 2022. If a board ships by the end of 2025 it will be doing very well.
- adgjlsfhk1 2y ago
  why does it take so long? I totally understand for leading edge products on new nodes why it would, but for chips on mature processes, what's the bottleneck between design and sale? I know the round trip time from the foundries is ~3 months. Is the rest validation? It feels like it would be really valuable to be able to reduce the time to ~1 year (even if that came at the cost of power, area or a moderate amount of performance). Shortening the feedback loop here would be super helpful for designers and programmers to be able to experiment with new paradigms faster I would think.
  - brucehoult 2y ago
    Largely because in the Arm and RISC-V worlds company A designs the CPU core, then at some point company B decides to license the core to make an SoC and starts designing it. Then company C manufactures the chip. Then when the chip is available companies D, E, F design boards for the chip to go on. Traditionally in x86 Intel and AMD do all the first three steps in one company, with the stages overlapped, and feedback. Also, Intel and AMD (and even more so Apple) don't announce a new chip until it is very close to shipping. They might have been working on it internally for five years before that. Arm and RISC-V companies have to make public announcements when a core is nearing design completion, to give a chance for companies such as Allwinner and Rockchip and Broadcom and Mediatek and Sophgo and Starfive to take a look at the specs and decide that it might be interesting to build a chip using that core. > I know the round trip time from the foundries is ~3 months. That's only if the chip works first time. Many don't and need several re-spins. I believe 3 or 4 is not uncommon. And variable amounts of re-design and re-layout and re-verify time between each of those ~3 months at the foundry. Given that, it would be a brave company that went straight to mass-production without a round of test chips first, so you've got 2x ~3 months, plus "bring up" time in between, even in the best case.

aseipp 2y ago

The only board that is cheap and available with the ratified 1.0 vector extension I know of is the Kendryte K230, which you can find on some boards for about $40 USD: https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html https://developer.canaan-creative.com/k230/dev/zh/00_hardwar... Note that it's only on one 1.6GHz core, and still pretty anemic otherwise (pi form factor, it's to be expected.) So something "deskop grade" with all the nice extensions and other goodies is probably still a ways off. Maybe next year; we'll have to see -- but lots of useful extensions continue to be ratified today, so it may still be a while before things "cool off."

mshockwave 2y ago
SpacemiT K1 on BananaPi is another commonly seen RVV 1.0 capable chip. IIRC both Kendryte K230 and SpacemiT K1 are in-order cores.

6SixTy 2y ago

it takes time (~2 years) for silicon designers to go from idea to taping out silicon. The P550's cores are advertised as having good area efficiency, so it could be both getting rid of the vector extensions to optimize area and they just couldn't incorporate them into the design. I is the base integer instructions M is integer multiplication A is atomic F is single precision float D is double precision G is shorthand for all of the above + 2 others that I honestly have no idea what they do

mshockwave 2y ago
> 2 others that I honestly have no idea what they do CSR (i.e. status) register and instruction fence extensions. Instruction fences are most useful in cases where you modify text section during runtime (e.g. JIT or code hot reload) such that you need to ensure the consistency of code across different harts
jecel 2y ago
> + 2 others that I honestly have no idea what they do The original RV32I and RV64I required some control registers for high frequency counters and instruction counters. You also needed the instructions to access these registers. This proved to be too complex for the simplest implementations, so recently (five years ago?) this functionality has been moved to their own extensions. Including these extensions in G makes the current G have the same functionality as the original G.
- snvzz 2y ago
  Important to highlight this happened before the base RISC-V specs were ratified. i.e. features have not been removed after ratification.
cmrdporcupine 2y ago
Ok, wow I didn't even clue in that the IMAFD was other extensions, and the G a "rollup" of them, because last time I played with RISC-V it was just with cores that did IMF