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The article hints at the ability to make multiple layers with a single lithography step. That seems incorrect based upon my mental model of how semiconductors a
by jmpman 2y ago
The article hints at the ability to make multiple layers with a single lithography step. That seems incorrect based upon my mental model of how semiconductors are typically manufactured. I’d expect a lithography process for every layer. Which one is correct?
- wtallis 2y ago3D NAND is built by depositing dozens of alternating layers, then etching tall, narrow vertical channels down through the stack. Those channels are filled in with other materials to form vertical strings of memory cells. The ability to make many layers of memory cells without needing lithography and etch per layer is the main reason why 3D NAND is so cost-effective and able to continue scaling in density far beyond what was achievable with planar NAND flash memory (which could only improve by making memory cells smaller, but they were getting too small to actually work). Intel's 3D XPoint memory (used in Optane products) was doomed in part by the fact that it did need lithography for every single layer, so it couldn't scale up in layer count cheaply.
- creer 2y ago> lithography process for every layer It's not. They are similar process steps, deposition, etching, etc but they are applied at once to long deep holes and other staircases that intersect the many layers. The layer is an insulator or conductor (etc) which intersects an entire plane of these tubes. Equals one planar wire which addresses one whole plane of tube intersections. So that's one of the problems in there: similar operations but applied in grossly different circumstances, but lots of unknowns and different ideas being thrown at the wall. And that's one of the opportunities: it's hard to tell how long this will work. Like, how many years of scaling this will produce.