Ryzen chips have a different network topology than Threadripper and EPYC chips. All external communication goes through the IO die, so any given core on either

Ryzen chips have a different network topology than Threadripper and EPYC chips. All external communication goes through the IO die, so any given core on either processor die is the same effective distance to the memory modules. The speed of signal propagation being finite, it's possible that individual cores within the same die might have different effective latencies, depending on how they routed the bus internally (although that's a problem you have on any single die multicore design), but it's not possible when comparing cores at mirrored positions on opposite dies. Threadripper and EPYC are totally different. They actually have NUMA topologies, where different dies are wired such that they have more distance to traverse to reach a given memory module, and accessing the farther ones involves some negotiation with a routing component.