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Chiplets don't require NUMA. The Ryzen 9s have their cores split between two chiplets and still have UMA. Of course, if you're on over a hundred cores you will

Chiplets don't require NUMA. The Ryzen 9s have their cores split between two chiplets and still have UMA. Of course, if you're on over a hundred cores you will be on a NUMA platform, but NUMA isn't really new, either, and has been around since at least the first multi-socket systems. Async/await isn't more of a problem with it than regular old preemption, and that has generally been solved through virtualization and/or per-process processor affinity.

bob1029 2y ago
> Chiplets don't require NUMA The nuance is that even if you "hide" the extra NUMA tier and have oversized lanes connecting everything, you still have some cores that are further away than others in time. It doesn't matter how it shows up in device manager, the physical constraint is still there.
- rowanG077 2y ago
  I don't see how the physical constraint matters of you can't observe it with a performance penalty. I don't really know if that's the case but that is what the person you are replying to is implying.
- fluoridation 2y ago
  Ryzen chips have a different network topology than Threadripper and EPYC chips. All external communication goes through the IO die, so any given core on either processor die is the same effective distance to the memory modules. The speed of signal propagation being finite, it's possible that individual cores within the same die might have different effective latencies, depending on how they routed the bus internally (although that's a problem you have on any single die multicore design), but it's not possible when comparing cores at mirrored positions on opposite dies. Threadripper and EPYC are totally different. They actually have NUMA topologies, where different dies are wired such that they have more distance to traverse to reach a given memory module, and accessing the farther ones involves some negotiation with a routing component.

bob1029 2y ago

> Chiplets don't require NUMA The nuance is that even if you "hide" the extra NUMA tier and have oversized lanes connecting everything, you still have some cores that are further away than others in time. It doesn't matter how it shows up in device manager, the physical constraint is still there.

rowanG077 2y ago
I don't see how the physical constraint matters of you can't observe it with a performance penalty. I don't really know if that's the case but that is what the person you are replying to is implying.
fluoridation 2y ago
Ryzen chips have a different network topology than Threadripper and EPYC chips. All external communication goes through the IO die, so any given core on either processor die is the same effective distance to the memory modules. The speed of signal propagation being finite, it's possible that individual cores within the same die might have different effective latencies, depending on how they routed the bus internally (although that's a problem you have on any single die multicore design), but it's not possible when comparing cores at mirrored positions on opposite dies. Threadripper and EPYC are totally different. They actually have NUMA topologies, where different dies are wired such that they have more distance to traverse to reach a given memory module, and accessing the farther ones involves some negotiation with a routing component.