I believe the first generation of Zen Epyc chips were designed to be scalable in the sense that each die had its own CCX, memory controllers, and serdes blocks

I believe the first generation of Zen Epyc chips were designed to be scalable in the sense that each die had its own CCX, memory controllers, and serdes blocks (for PCIe, SATA, and 10GKR). A single die Epyc was a single NUMA node, dual die Epyc were 2 NUMA nodes, and quad die Epycs were 4 NUMA nodes. It really was that all the resources from the other dies were in other NUMA nodes. Accessing another die's caches, memory controllers, or serdes blocks required using the infinity fabric. In later generations of Zen Epyc CPUs, there's a central IO die which has the memory controllers and serdes blocks, then small CCX dies which effectively just had CPU cores and caches on them. This allowed for using different process nodes or manufacturing technologies to optimize for each die's specific tasks. It also allowed for much more modular configurations of CPU core counts and CPU frequencies while providing a high number of memory controllers and serdes lanes, to address different market desires.