4 ms·
"Short reasons for long vectors in HPC CPUs: a study based on RISC-V": https://arxiv.org/abs/2309.06865 https://arxiv.org/abs/2309.06865 Suggests that VLEN>DLE
by camel-cdr 2y ago
"Short reasons for long vectors in HPC CPUs: a study based on RISC-V": https://arxiv.org/abs/2309.06865 https://arxiv.org/abs/2309.06865
Suggests that VLEN>DLEN can help hide the memory latency.
"Instruction Scheduling in the Saturn Vector Unit": https://arxiv.org/html/2412.00997v1 https://arxiv.org/html/2412.00997v1
> VII-A Chime Length
> The “native” chime length in Saturn, for instructions with no register grouping, is given by the VLEN:DLEN ratio. Increasing the native chime length reduces overall throughput pressure on many components in Saturn, including instruction fetch, load-store queue sizes, issue-queue sizes, and sequencer throughput.
> However, a higher native chime length for a constant datapath linearly scales the size of the multi-ported register file. The interlock logic in Saturn scales linearly with the chime length as well. We evaluate several configurations with varying VLEN:DLEN ratios, varying VLEN with fixed DLEN=256. As we increment the VLEN:DLEN ratio, we record the percent improvement in performance for each kernel. Table IV depicts the results of this comparison.
> A native chime length of 1 imposes a very high performance burden, as this implementation effectively requires 1 IPC instruction issue when executing non-register-grouped code. Moving a 2:1 ratio yields significant performance improvements across most kernels, as greater chime lengths diminish the performance impact of scalar stalls. A 2:1 ratio is feasible with the precise scheduling mechanism and is the target design point for Saturn.
> The effect is largely diminished at a 4:1 ratio, where only a few low-LMUL kernels see the benefit. We additionally observe that some benchmarks actually exhibit performance degradation at high chime lengths. Analysis of these cases revealed that deep temporal execution diminishes the effectiveness of load balancing across issue paths. These cases exposed a performance peculiarity specific to our evaluation system’s memory system: the evaluated LLC achieves higher throughput with a dynamic mix of loads and stores, compared to separate load-intensive and store-intensive phases.