In reading further, I found an FPGA routing contest[1] this responded to, and I can't possibly store that much abstraction in my stack. I'm amazed that anything

In reading further, I found an FPGA routing contest[1] this responded to, and I can't possibly store that much abstraction in my stack. I'm amazed that anything ever gets done with FPGAs. My ideal FPGA isn't... it's a systolic array of latched LUTs that's almost trivial to route. [1] https://xilinx.github.io/fpga24_routing_contest/index.html https://xilinx.github.io/fpga24_routing_contest/index.html