Yes, nothing here is really new. For inference, trits/sec decoded into L1 cache is a lot more important than random access, and is going to be hardware specifi

Yes, nothing here is really new. For inference, trits/sec decoded into L1 cache is a lot more important than random access, and is going to be hardware specific (e.g. what SIMD instructions are available). 8bit seems an odd choice given most available instructions, but the Succincter paper's use of mod and individual decoding is (unless I am misreading it) much slower.