4 ms·
Interesting that in the Cortex-A15 this is a "key design feature". Are there any numbers about its effect other chips? I guess this could also be used as an op
by fulafel 2y ago
Interesting that in the Cortex-A15 this is a "key design feature". Are there any numbers about its effect other chips?
I guess this could also be used as an optimization target at least on devices that are more long lived designs (eg consoles).
- nwallin 2y agoI'm curious about this too. I would expect any RISC architecture to gain relatively little from a loop buffer. The point of RISC is that instruction fetch/decode is substantially easier, if not trivial.