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It's not the wafer cost. The masks (the "negatives" for the lithography) are the problem. A mask set (you need multiple exposures for one device) for a modern E
by lobochrome 2y ago
It's not the wafer cost. The masks (the "negatives" for the lithography) are the problem. A mask set (you need multiple exposures for one device) for a modern EUV node costs 20-30m$. That's the limiting factor. You can't get cheaper than that.
As a sibling comment notes, multi-product wafers are a theoretical answer. However, since you have process corners (manufacturing defects aren't uniformly distributed on the wafer), it is unfeasible for anything but the cheapest parts.
The real next moonshot in the foundry business would be to lower the respin costs, i.e., the amount of money it costs when your fabbed first silicon doesn't yield or validate functionally in the way you had expected/planned.
If I were the US government (or any other), I'd focus on that. Subsidize the respin cost to zero in the short-term, given certain prerequisites for start-ups, and push an all-out Manhatten project RnD effort to lower the respin cost in the long run.
- richk449 2y agoMultibeam corporation is making “maskless” lithography tools: https://multibeamcorp.com/applications/#high-value https://multibeamcorp.com/applications/#high-value
- ChuckMcM 2y agoI get that for state of the art fabs. Those optimize for long runs on big wafers. My question though is can you find a solution at a different node which favors cost/turnaround at the expense of not scaling? For example, could one make a 200nm node with conventional UV masks and a limit of say 10 layers? Non mask lithography options? Or as in the article 'sub' masks where you step a single die image across the wafer?
- MichaelZuo 2y agoEven a 10x cheaper mask set would still be $2-3 million USD.
- morcheeba 2y ago>lower the respin costs You might be interested in structured ASICs, which allow for substantial reuse of masks between different products. At the extreme was a via-only definition product where all interconnects were specified with one mask (and the via masks were among the cheapest to make since they are very uniform). In regular ASIC development, we've had extra unrouted transistors available to wire in case of a mistake (so hopefully the respin involved just some new metal layers). Techniques like FIB can be used to test fixes to lower the number of respins, too. I'm not sure how much of this was automated to maximize chances of being useful. https://en.wikipedia.org/wiki/Structured_ASIC_platform https://en.wikipedia.org/wiki/Structured_ASIC_platform
- mjevans 2y agoMasks make sense the same way mega-print runs with similar fixed plates / other high yield copy operations make sense. Offhand I'm not aware of a chip fab tech similar to the Laser Printer, not in a literal laser used to print but in a 'low run of tolerable quality' approach. The equivalent to a small print shop locally that has a medium-small range printer that does not use masks but churns out at high quality and speed.
- niccl 2y agoIsn't Electron Beam Lithography [0] that sort of thing? slow, obviously, and I'm not sure about resolution, 0: https://en.wikipedia.org/wiki/Electron-beam_lithography https://en.wikipedia.org/wiki/Electron-beam_lithography
- lobochrome 2y agoIt is. Unfortunately it never worked at scale.