We also have been developing six kinds of reconfigurable processors (Morphle engine and SiliconSqueak) for our Wafer Scale Integration since 2008. A little info

We also have been developing six kinds of reconfigurable processors (Morphle engine and SiliconSqueak) for our Wafer Scale Integration since 2008. A little information and slides can be found in the four hour talk [1] and in our papers since 2008 [2,3]. Our runtime reconfigurability comes from adaptive [5] load-balancing [1] JIT compilers (at runtime) that reconfigure hardware or generate hardware blocks at runtime with Morphle Logic [4]. We have 8-bit slices that you can combine per [block of] instructions into teams to make CPU or GPU or DSP or TPU cores and fine grained logic cells to make FPGA fabric and interconnect networks. Like Transmeta and Apple Silicon our processors also are optimized to emulate bytecode, Intel, ARM and RISC-V instructions. With large teams of 80 8-bit slices we can emulate Intel instruction blocks several times faster than high-end Xeon or AMD ZEN 4 cores can run them. [1] https://vimeo.com/731037615 https://vimeo.com/731037615 [2] https://scholar.google.com/citations?user=mWS92YsAAAAJ&hl=en&oi=ao https://scholar.google.com/citations?user=mWS92YsAAAAJ&hl=en... [3] https://scholar.google.com/citations?user=6wa49gkAAAAJ&hl=en https://scholar.google.com/citations?user=6wa49gkAAAAJ&hl=en [4] https://github.com/fiberhood/MorphleLogic/blob/main/README_MORPHLE_LOGIC.md?plain=1 https://github.com/fiberhood/MorphleLogic/blob/main/README_M... [5] https://youtu.be/CfYnzVxdwZE https://youtu.be/CfYnzVxdwZE