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Hynix launches 321-layer NAND
- pajeetz 2y agoinsider info: all the top talent at Samsung left for SK Hynix after government stepped and forced DEI on Samsung leading to unqualified managers ruining Samsung's culture of innovation and rewarding experimentation.
- AlbertoGP 2y agoWhen did this happen?
- kridsdale3 2y agoWhen I was in school studying NAND devices (2004-2010) we were quite apprehensive at the long term quantum stability of 4-layer devices. This (the past 20 years of improvement) is an incredible feat of engineering.
- duskwuff 2y agoThis is 321 physical layers of silicon in an IC, not 321 charge levels. QLC flash - with 16 charge levels, for four bits per cell - is pretty common nowadays, but that's as far as it goes so far. And stability is indeed a concern; modern flash devices rely heavily on error correction.
- cma 2y agoMemory like HBM uses stacking of silicon layers, but NAND flash isn't layers of silicon, it's other materials for capturing and holding charge with still just one silicon plane it's all built on top of I believe.
- hinkley 2y agoWhere’s the point where you figure out how to stack chiplets perpendicular to a backplane instead of doing lithography 300 times on the same chip?
- duskwuff 2y agoThat's kind of what we're doing already, although the stacking is parallel, not perpendicular. A lot of the innovation is in how the dies are tied together, cf. https://www.anandtech.com/show/9520/toshiba-brings-throughsilicon-vias-to-nand-flash https://www.anandtech.com/show/9520/toshiba-brings-throughsi...
- creer 2y agoThis is an interesting testament to manufacturing reliability - that they can go to so many layers and still achieve good yield.
- mlyle 2y agoAs others here have pointed out -- you don't need to do lithography 300 times. The big breakthrough of 3D NAND is depositing alternating layers of films to build most of the layers. This is 3 stacks of >100 layers.
- fodkodrasz 2y ago> triple level cell-based 4D memory What does 4D memory mean?
- matja 2y agoNothing - just marketing. It's their 2nd gen Periphery Under Cell (PUC) device.
- baybal2 2y ago[dead]
- wrs 2y agoIt’s marketing speak. 3D flash (stacked chips) with the control circuits stacked underneath instead of to the side. So it’s one louder. https://www.tomshardware.com/news/sk_hynix-debuts-4d_nand,37565.html https://www.tomshardware.com/news/sk_hynix-debuts-4d_nand,37...
- K0HAX 2y agoBigger number = more betterer
- tbrownaw 2y agoIt'd have to be something involving time... maybe have each cell be a delay line? Or a resonant cavity, and store multiple bits at different modes? Not sure how either could be made small enough to be worth it though...
- Animats 2y agoWow. What's the yield like? Are some bits bad and bypassed during testing?
- timschmidt 2y ago> Are some bits bad and bypassed during testing? Always. All digital storage media depends on error correcting codes and sector-remapping these days.
- Neywiny 2y agoI just want smaller SPI flash for embedded :( it's been over 10 years since there's been improvement in that space
- duskwuff 2y agoWLCSP-8 is pretty damn small already, at ~1.5mm square. Hard to get much smaller.
- Neywiny 2y agoBut they aren't high capacity. As far as I've seen, we've been stuck on the same XY size 512 Mb dies for over a decade. Even now, Infineon is claiming they have a series that'll go up to 4 Gb but is still at the standard 2 Gb maximum. NOR hasn't gotten any denser in forever.
- duskwuff 2y agoWhat's the use case for a NOR flash that large? Even at 2 Gbit, you're probably better off with something optimized for density like eMMC.
- Neywiny 2y agoThe use is that there's often (in my field) no space for an 11.5x13 eMMC. There are some that are slightly smaller, but as you brought up the wlcsp-8, there's nothing like eMMC/high capacity NAND density scaled down. If I had the bits/mm^2 of even NAND 5 years ago, I'd be a happy camper. But that's life.
- mlyle 2y agoThere's QSPI NAND parts available; they're just annoying to use. https://www.digikey.com/en/products/detail/winbond-electronics/W25N04KVZEIR-TR/15181925 https://www.digikey.com/en/products/detail/winbond-electroni... https://www.digikey.com/en/products/detail/alliance-memory-inc/AS5F18G04SND-10LIN/13282906 https://www.digikey.com/en/products/detail/alliance-memory-i... There's also 9x8mm eMMC. The big issue with shrinking it further is that it tends to be a module with a separate controller doing lots of things to make the memory reasonable to use.
- tomcam 2y agoCookie permission dialog is the worst I have encountered in months
- randomjoe2 2y agoThank god for ublock origin filters, i have all the optional filter lists, I never see those things. EVER.
- CoastalCoder 2y agoI noticed that as well. I'm not sure what the rules are, but I had to disable a surprising number of "legitimate interests" related to advertising.
- StringyBob 2y agoWhat does 'layer' mean in this context? I'm only familiar with planar style logic process nodes which have maybe up to 20 layers (and way more lithography steps to manufacture those layers), but I am completely ignorant of how the term is used for a flash process node. How many layers are needed for each physical cell? Is it 1,2, or a lot more? Is this effectively 321 physical TLC cells stacked vertically and some planar style logic at the bottom of the stack. Also, where do multiple pieces of silicon factor into this - I assume we might be up to 16 silicon dies deep with through-silicon-vias, which would mean a cross section of a package could actually have 5000 layers - that sounds crazy!
- brennanpeterson 2y agoProbably done with 3 separate litho/etch layers, where they etch and process in groups of 110 or so. Each of those layers can have a cell, so if you have a tlc device at a 100nm pitch, you have a density of 321*3/(1e-4)^2 bits/mm, or about 1e11bits/mm2. Fun reference: atomic density is 1atom/.5nm, so 1/5e-7^2, or 4e12/mm2 ish. Not too far away.
- StringyBob 2y agoAmazing, I had no idea how far things had diverged between logic and flash since the move to 3D. https://borecraft.com/files/Comparison_Current_NAND.pdf https://borecraft.com/files/Comparison_Current_NAND.pdf (from 2019) has some of the cross-sections I was looking for - and that only goes up to 96 layers!
- RicoElectrico 2y agoWhat's interesting is that these devices don't need 321+ litho steps; the vertical layers are all defined with deposition. Lithography step count isn't layer dependent it seems. https://youtu.be/ANHzVOiUwGI https://youtu.be/ANHzVOiUwGI https://thememoryguy.com/3d-nands-impact-on-the-equipment-market/ https://thememoryguy.com/3d-nands-impact-on-the-equipment-ma...
- drpixie 2y agoTitle should probably be "Hynix launches 321-layer NAND RAM".
- FabHK 2y agoI think it might be flash memory (i.e. non-volatile, unlike RAM), but this must be so obvious to readers of this publication that it's never said explicitly.
- ksec 2y agoIf I am reading this correctly, this is still the same 1Tb per die but with 321 layers, meaning up to 2TB / package. The package should now be under 100mm2. This would hopefully bring down the price of 4TB and 8TB SSD in the near future.