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TSO toggle on Apple Silicon is a user-space accessible/writable register. It is used when you install rosetta2 for Linux VMs https://developer.apple.com/docum

by zeusk 2y ago

TSO toggle on Apple Silicon is a user-space accessible/writable register. It is used when you install rosetta2 for Linux VMs https://developer.apple.com/documentation/virtualization/running_intel_binaries_in_linux_vms_with_rosetta https://developer.apple.com/documentation/virtualization/run...

Syonyk 2y ago
Are you sure it's userspace accessible? Based on https://github.com/saagarjha/TSOEnabler/blob/master/TSOEnabler/TSOEnabler.c https://github.com/saagarjha/TSOEnabler/blob/master/TSOEnabl..., it's a field in ACTLR_EL1, which is explicitly (per the ARMv8 spec, at least...) not accessible to userspace (EL0) execution. There may be some kernel interface to allow userspace to toggle that, but that's not the same as being a userspace-accessible SCR (and I also wouldn't expect it to be passed through to a VM - you'd likely need a hypercall to toggle it, unless the hypervisor emulated that, though admittedly I'm not quite as deep weeds on ARMv8 virtualization as I would prefer at the moment.
- zeusk 2y ago
  Hmm, you’re right - maybe my memory serves incorrectly but yeah it seems it is privileged access but the interface is open to all processes to toggle the bit.
shadowfacts 2y ago
It is not directly accessible from user-space. Making it so requires kernel support. Apple published a set of patches for doing this on Linux: https://developer.apple.com/documentation/virtualization/accelerating_the_performance_of_rosetta https://developer.apple.com/documentation/virtualization/acc... Without that kernel support, all processes in the VM (not just Rosetta-translated ones) are opted-in to TSO: > Without selective enablement, the system opts all processes into this memory mode [TSO], which degrades performance for native ARM processes that don’t need it.
- mrpippy 2y ago
  Before Sequoia, a Linux VM using Rosetta would have TSO enabled all the time. With Sequoia, TSO is not enabled for Linux VMs, and that kernel patch (posted in the last few weeks) is required for Rosetta to be able to enable TSO for itself. If the kernel patch isn't present, Rosetta has a non-TSO fallback mode.

by zeusk 2y ago

Syonyk 2y ago

Are you sure it's userspace accessible? Based on https://github.com/saagarjha/TSOEnabler/blob/master/TSOEnabler/TSOEnabler.c https://github.com/saagarjha/TSOEnabler/blob/master/TSOEnabl..., it's a field in ACTLR_EL1, which is explicitly (per the ARMv8 spec, at least...) not accessible to userspace (EL0) execution. There may be some kernel interface to allow userspace to toggle that, but that's not the same as being a userspace-accessible SCR (and I also wouldn't expect it to be passed through to a VM - you'd likely need a hypercall to toggle it, unless the hypervisor emulated that, though admittedly I'm not quite as deep weeds on ARMv8 virtualization as I would prefer at the moment.

zeusk 2y ago
Hmm, you’re right - maybe my memory serves incorrectly but yeah it seems it is privileged access but the interface is open to all processes to toggle the bit.

shadowfacts 2y ago

It is not directly accessible from user-space. Making it so requires kernel support. Apple published a set of patches for doing this on Linux: https://developer.apple.com/documentation/virtualization/accelerating_the_performance_of_rosetta https://developer.apple.com/documentation/virtualization/acc... Without that kernel support, all processes in the VM (not just Rosetta-translated ones) are opted-in to TSO: > Without selective enablement, the system opts all processes into this memory mode [TSO], which degrades performance for native ARM processes that don’t need it.

mrpippy 2y ago
Before Sequoia, a Linux VM using Rosetta would have TSO enabled all the time. With Sequoia, TSO is not enabled for Linux VMs, and that kernel patch (posted in the last few weeks) is required for Rosetta to be able to enable TSO for itself. If the kernel patch isn't present, Rosetta has a non-TSO fallback mode.