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Does Windows's translation take advantage of those where they exist? E.g. if I launch an aarch64 Windows VM on my M2, does it use the M2's support for TSO when
by scottlamb 2y ago
Does Windows's translation take advantage of those where they exist? E.g. if I launch an aarch64 Windows VM on my M2, does it use the M2's support for TSO when running x86_64 .exes or does it insert these memory barriers?
If not, it makes sense that Qualcomm didn't bother adding them.
- Syonyk 2y agoI would expect it to not use TSO, because the toggle for it isn't, to the best of my knowledge, a general userspace toggle. It's something the kernel has to toggle, and so a VM may or may not (probably does not) even have access to the SCRs (system control registers) to change it.
- zeusk 2y agoTSO toggle on Apple Silicon is a user-space accessible/writable register. It is used when you install rosetta2 for Linux VMs https://developer.apple.com/documentation/virtualization/running_intel_binaries_in_linux_vms_with_rosetta https://developer.apple.com/documentation/virtualization/run...
- Syonyk 2y agoAre you sure it's userspace accessible? Based on https://github.com/saagarjha/TSOEnabler/blob/master/TSOEnabler/TSOEnabler.c https://github.com/saagarjha/TSOEnabler/blob/master/TSOEnabl..., it's a field in ACTLR_EL1, which is explicitly (per the ARMv8 spec, at least...) not accessible to userspace (EL0) execution. There may be some kernel interface to allow userspace to toggle that, but that's not the same as being a userspace-accessible SCR (and I also wouldn't expect it to be passed through to a VM - you'd likely need a hypercall to toggle it, unless the hypervisor emulated that, though admittedly I'm not quite as deep weeds on ARMv8 virtualization as I would prefer at the moment.
- zeusk 2y agoHmm, you’re right - maybe my memory serves incorrectly but yeah it seems it is privileged access but the interface is open to all processes to toggle the bit.
- shadowfacts 2y agoIt is not directly accessible from user-space. Making it so requires kernel support. Apple published a set of patches for doing this on Linux: https://developer.apple.com/documentation/virtualization/accelerating_the_performance_of_rosetta https://developer.apple.com/documentation/virtualization/acc... Without that kernel support, all processes in the VM (not just Rosetta-translated ones) are opted-in to TSO: > Without selective enablement, the system opts all processes into this memory mode [TSO], which degrades performance for native ARM processes that don’t need it.
- mrpippy 2y agoBefore Sequoia, a Linux VM using Rosetta would have TSO enabled all the time. With Sequoia, TSO is not enabled for Linux VMs, and that kernel patch (posted in the last few weeks) is required for Rosetta to be able to enable TSO for itself. If the kernel patch isn't present, Rosetta has a non-TSO fallback mode.
- saagarjha 2y agoThis is exposed to guest kernels of Sequoia (and maybe earlier?).
- zeusk 2y agoThe OS can use what hardware supports, Mac OS does because SEG is a tightly integrated group at Apple whereas Microsoft treats hardware vendors at arm's length (pun unintended). There are roadmap sharing, planning events through leadership but it is not as cohesive as it is at Apple.
- saagarjha 2y agoNo because Windows is not aware of how Apple does it. There exist Linux patches documenting how to do so, though.
- scottlamb 2y agoThe article says the following: > As far as I know this is not part of the ARM standard, but it also isn’t Apple specific: Nvidia Denver/Carmel and Fujitsu A64fx are other 64-bit ARM processors that also implement TSO (thanks to marcan for these details). I'm not sure how to interpret that—do these other parameters have distinct/proprietary TSO extensions? Are they referring to a single published (optional) extension that all three implement? The linked tweet has been deleted so no clues there, and I stopped digging.
- saagarjha 2y agoThose are just TSO all the time I think. So they are stronger than the ARM requirement