3 ms·
They are doing it with custom silicon with several times more area than 8x H100s. I’m sure they are doing some sort of optimization at execution/runtime, but t
by parsimo2010 2y ago
They are doing it with custom silicon with several times more area than 8x H100s. I’m sure they are doing some sort of optimization at execution/runtime, but the primary difference is the sheer transistor count.
https://cerebras.ai/product-chip/ https://cerebras.ai/product-chip/
- coder543 2y agoTo be specific, a single WSE-3 has the same die area as about 57 H100s. It's a big chip.
- deleted 2y ago[deleted]
- cma 2y agoIt is worth splitting out the stacked memory silicon layers on both too (if Cerebras is set up with external DRAM memory). HBM is over 10 layers now so the die area is a good bit more than the chip area, but different process nodes are involved.
- tomrod 2y agoAmazing!
- deleted 2y ago[deleted]