2 ms·
This may come largely from clock speed needing disproportionately more/less energy the higher/lower it goes. This answer (based on an old source) even says pow
by cubefox 2y ago
This may come largely from clock speed needing disproportionately more/less energy the higher/lower it goes.
This answer (based on an old source) even says power consumption increases with the cube of the clock speed: https://physics.stackexchange.com/posts/61937/revisions https://physics.stackexchange.com/posts/61937/revisions
Though this would mean a 4x in clock speed would consume 4^3=64 times as much energy, which is more extreme than what is observed here in the Apple chip. So either the clock speed/power relation is different now or the P cores do not actually have a 4x scaling in clock speed. Cache size etc may also play a role in performance.
- huijzer 2y agoIsn't that called Dennard scaling [1]? [1]: https://en.wikipedia.org/wiki/Dennard_scaling https://en.wikipedia.org/wiki/Dennard_scaling
- cubefox 2y agoNo, the "cube law" is related to varying clock speed rather than to varying transistor size.
- formerly_proven 2y agoPer the article, the clock speed difference is much smaller than the ~4x performance difference (4.5 GHz vs 2.6 GHz, i.e. 1.7x). So more than half of the performance advantage of the P cores has to come out of the uarch difference (wider structures etc.). Meanwhile there will be other factors besides clock frequency, e.g. the P cores might use a different cell library than the E cores.
- cubefox 2y agoMakes sense. This would suggest the difference in power draw may not mainly come from the clock frequency, since (1.7x)^3=5x, which is significantly less than the 13.5x in power draw.