8 ms·

I wonder what changes? In-order vs OOO? Less int/fp units? Are they fully instruction set compatible?

nsbk 2y ago
From the article about the instruction set: > This is believed to be identical to ARMv9.2-A without Scalable Vector Extension (SVE) supported by M4 P cores, enabling the same threads to be run on either core type. It also explicitly mentions half of the processing units per core and lower clock speeds.
saagarjha 2y ago
No, yes, yes
whereismyacc 2y ago
Isn't basically every modern cpu core OOO?
bayindirh 2y ago
No they are not. "Efficiency" cores are generally tailored to do simple stuff well. Less floating point, more integers. Like file parsing, serving web pages, responding to network events, whatnot. When you need heavy computation (encoding, scientific, etc.) P cores are your only choices. As a result, server ecosystem will be fragmented a bit. For HPC and calculation stuff, P-Core heavy processors will be sold. For cloud and CRUD systems, E-Cores will dominate.
- formerly_proven 2y ago
  Curiously we had this argument before, roughly two decades ago.
  - bayindirh 2y ago
    Doesn't this happen in cycles? A specialized hardware appears, then it gets integrated into processor to make way for an even more specialized variant of the thing, rinse and repeat. This external thing doesn't have to be "more powerful" per se. So, E cores are lower power helpers which are implemented back into the CPU in a slightly altered form. Who or which prevents them from being dedicated to processing a network stream or just handling network thread of a service, making them "efficient accelerators" in a sense?
- JohnBooty 2y ago
  From the article: "[The E cores'] instruction set is the same as M4 P cores, ARMv9.2-A without its Scalable Vector Extension (SVE)"
  - bayindirh 2y ago
    I mean, not having the SVE do not make them run all the workload of P cores, and this is what I said already? They are not of course different ISAs at the core, but they're not the same cores per se. When you are missing extensions, you can't address these cores when there are these instructions present. Forcing it, would kill your application with an illegal instruction error. So heavy computational stuff is not the target of E cores, you need P cores for that.
    - aseipp 2y ago
      The quoted sentence is poorly worded. The P and E cores are fully instruction set compatible. It isn't possible to meaningfully know ahead of time if the instructions will be used on any given core, and trapping along with a migration is expensive and needless. The M4 as a whole does not support the SVE/SVE2 extensions anywhere, which is what the article is saying in the given quote. The M4, on all cores, does support the SME extension, which includes a subset of SVE instructions at a wider vector length (512-bits), optimized for throughput. SME instructions are handled by a separate accelerator coprocessor unit attached to each cluster, shared by a number of cores, and don't "exist" in the normal instruction pipeline (where e.g. 256-bit SVE2 instructions would be handled.) This was all true of the proprietary Apple AMX extensions in previous cores as well, as far as I'm aware.
- deleted 2y ago
  [deleted]

nsbk 2y ago

From the article about the instruction set: > This is believed to be identical to ARMv9.2-A without Scalable Vector Extension (SVE) supported by M4 P cores, enabling the same threads to be run on either core type. It also explicitly mentions half of the processing units per core and lower clock speeds.

saagarjha 2y ago

No, yes, yes

whereismyacc 2y ago

Isn't basically every modern cpu core OOO?

bayindirh 2y ago

No they are not. "Efficiency" cores are generally tailored to do simple stuff well. Less floating point, more integers. Like file parsing, serving web pages, responding to network events, whatnot. When you need heavy computation (encoding, scientific, etc.) P cores are your only choices. As a result, server ecosystem will be fragmented a bit. For HPC and calculation stuff, P-Core heavy processors will be sold. For cloud and CRUD systems, E-Cores will dominate.

formerly_proven 2y ago
Curiously we had this argument before, roughly two decades ago.
- bayindirh 2y ago
  Doesn't this happen in cycles? A specialized hardware appears, then it gets integrated into processor to make way for an even more specialized variant of the thing, rinse and repeat. This external thing doesn't have to be "more powerful" per se. So, E cores are lower power helpers which are implemented back into the CPU in a slightly altered form. Who or which prevents them from being dedicated to processing a network stream or just handling network thread of a service, making them "efficient accelerators" in a sense?
JohnBooty 2y ago
From the article: "[The E cores'] instruction set is the same as M4 P cores, ARMv9.2-A without its Scalable Vector Extension (SVE)"
- bayindirh 2y ago
  I mean, not having the SVE do not make them run all the workload of P cores, and this is what I said already? They are not of course different ISAs at the core, but they're not the same cores per se. When you are missing extensions, you can't address these cores when there are these instructions present. Forcing it, would kill your application with an illegal instruction error. So heavy computational stuff is not the target of E cores, you need P cores for that.
  - aseipp 2y ago
    The quoted sentence is poorly worded. The P and E cores are fully instruction set compatible. It isn't possible to meaningfully know ahead of time if the instructions will be used on any given core, and trapping along with a migration is expensive and needless. The M4 as a whole does not support the SVE/SVE2 extensions anywhere, which is what the article is saying in the given quote. The M4, on all cores, does support the SME extension, which includes a subset of SVE instructions at a wider vector length (512-bits), optimized for throughput. SME instructions are handled by a separate accelerator coprocessor unit attached to each cluster, shared by a number of cores, and don't "exist" in the normal instruction pipeline (where e.g. 256-bit SVE2 instructions would be handled.) This was all true of the proprietary Apple AMX extensions in previous cores as well, as far as I'm aware.
deleted 2y ago
[deleted]