>There is a LAN chip on the board but it should be left out, my tests were not great, it seems to cause stability issues in the system - reset (and COM1_CS/RTC

>There is a LAN chip on the board but it should be left out, my tests were not great, it seems to cause stability issues in the system - reset (and COM1_CS/RTC_DS) is routed horizontally across the board on inner layer cutting ground plane in half right under Realtek and both CPLDs :o. Weak stitching top layer islands using sparse tiny high impedance Vias is not a good way of joining isolated grounds. - only one Realtek VDD pin 17 is connected to power plane with thick via, rest are using tiny signal vias. - one tht 100nF capacitor might not be enough to decouple Realtek, usually on ISA cards there are pairs of caps for every one of RTL8019 six VDD inputs. Personally I think 12 caps is total overkill, but there is some middle ground in between. - Realtek differential TX output is routed along whole ISA J7 slot between pins, seemingly not a problem except it also goes between crystal pins (with interrupted ground, big no no) and over SD8-15 with no ground plane under. Once again ground plane is disrupted by signals being routed in it. This might lead to for example 20 MHz clock being coupled to upper part of data bus. - looks like 1.8432M for UART also goes across whole board with no ground plane in places. >In GitHub there are separate projects published for each of my design iterations. Would it be possible to upload whole kicad project (pcb, sch)? Much easier to browse than gerbers re-imported into pcbnew. - Whats the deal with RTC_CS from POWER_GOOD? Why additional redundant hex inverter generator for 32KHz? - Power and reset generation seems very elaborate, 6 chips doing the work of two 7404 inverters and few RC pairs. Am I correct in assuming those are leftovers from experimentation? Btw calling VBAT "VDD" was a funny trap, took me a good second to realize what was going on :) If you ever plan adding DRAM or Cache Im happy to help. My hobby dabbling https://github.com/raszpl/FIC-486-GAC-2-Cache-Module https://github.com/raszpl/FIC-486-GAC-2-Cache-Module https://github.com/raszpl/386RC-16 https://github.com/raszpl/386RC-16