The current design uses several CPLD for address decoding instead of original parts. An FPGA is planned for the remaining AT controllers, which are now hard to

The current design uses several CPLD for address decoding instead of original parts. An FPGA is planned for the remaining AT controllers, which are now hard to source: - the 2x 8237 DMA controller - the 2x 8259 Interrupt controller - the 8254 System timer This will allow anyone to build a modern AT, like this was done for the XT. Follow the discussion here: https://forum.vcfed.org/index.php?threads/project-to-create-an-atx-80286-mainboard-based-on-the-ibm-5170.1243108/page-27 https://forum.vcfed.org/index.php?threads/project-to-create-...