4 ms·
> Ideally, your working set fits into the cache Ideally, your working set fits into the registers, and that was most win feature or RISC, having relatively sim
by simne 2y ago
> Ideally, your working set fits into the cache
Ideally, your working set fits into the registers, and that was most win feature or RISC, having relatively simple hardware (if compared to genuine CISC, like IBM-360 mainframes) they saved significant space on chip for more registers.
- Register-register operations are definitely avoid memory wall, so data cache become insignificant.
Sure, if we compare comparable, not apples vs carrots.
- simne 2y agoIf you are unlucky, so your working set don't fit into the registers, in this case you sure will deal with memory bus and with cache hierarchy. But best if you just don't touch memory at all, making all processing in your code in registers.