3 ms·
I don’t think that’s correct. Ideally, your working set fits into the cache, and that doesn’t get smaller or larger when you use a RISC CPU. (There may be an e
by Someone 2y ago
I don’t think that’s correct. Ideally, your working set fits into the cache, and that doesn’t get smaller or larger when you use a RISC CPU.
(There may be an effect because of instruction density, but that’s not very big, and will have less of an effect the larger your working set)
- simne 2y ago> Ideally, your working set fits into the cache Ideally, your working set fits into the registers, and that was most win feature or RISC, having relatively simple hardware (if compared to genuine CISC, like IBM-360 mainframes) they saved significant space on chip for more registers. - Register-register operations are definitely avoid memory wall, so data cache become insignificant. Sure, if we compare comparable, not apples vs carrots.
- simne 2y agoIf you are unlucky, so your working set don't fit into the registers, in this case you sure will deal with memory bus and with cache hierarchy. But best if you just don't touch memory at all, making all processing in your code in registers.