3 ms·

Sorry to burst your bubble but modern FPGAs are already designed this way (latches paired with muxes and LUTs across the lattice). Take a look at the specs for

Sorry to burst your bubble but modern FPGAs are already designed this way (latches paired with muxes and LUTs across the lattice). Take a look at the specs for a Xilinx Spartan variant. You still need the routing bits because clock skew and propagation delay are real problems in large circuits.

mikewarot 2y ago
Yes, I know about clock skew and FPGAs. They are an optimization for latency, which can be quite substantial and make/break applications. The goal of an FPGA is to get a signal through the chip in as few nanoSeconds as possible. It would be insane to rip out that hardware in that case. However.... I care about throughput, and latency usually doesn't matter much. In many cases, you could tolerate startup delays in the milliseconds. Because everything is latched, clock skew isn't really an issue. All of the lines carrying data are short, VERY short, thus lower capacitance. I believe it'll be possible to bring the clock rates up into the Gigahertz. I think it'll be possible to push 500 Mhz on the Skywater 130 process that Tiny Tapeout uses. (Not outside of the chip, of course, but internally) [edit/append] Once you've got a working BitGrid chip rated for a given clock rate, it doesn't matter how you program it, because all logic is latched, the clock skew will always be within bounds. With an FPGA, you've got to run simulations, adjust timings, etc and wait for things to compile and optimize to fit the chip, this can sometimes take a day.
- glitchc 2y ago
  Latency is only part of the problem. Unmanaged clock skew leads to race conditions, dramatically impacting circuit behaviour and reliability. That's the reason the industry overwhelmingly uses synchronized circuit designs and clocks to trigger transitions.
- simne 2y ago
  The goal of an FPGA is to get cheap prototype and/or for applications which don't need large batches, enough to ASIC become cost effective. Low latency links are just byproduct, added to improve FPGA performance (which is definitely bad if compare to ASIC), you don't have to use them in your design. If you will make working FPGA prototype, it would be not hard to convert them to ASIC. Happy birthday!
- simne 2y ago
  BTW have you hear about asynchronous FPGA programming (and asynchronous HDL design)? It was very popular subject some years ago.

mikewarot 2y ago

Yes, I know about clock skew and FPGAs. They are an optimization for latency, which can be quite substantial and make/break applications. The goal of an FPGA is to get a signal through the chip in as few nanoSeconds as possible. It would be insane to rip out that hardware in that case. However.... I care about throughput, and latency usually doesn't matter much. In many cases, you could tolerate startup delays in the milliseconds. Because everything is latched, clock skew isn't really an issue. All of the lines carrying data are short, VERY short, thus lower capacitance. I believe it'll be possible to bring the clock rates up into the Gigahertz. I think it'll be possible to push 500 Mhz on the Skywater 130 process that Tiny Tapeout uses. (Not outside of the chip, of course, but internally) [edit/append] Once you've got a working BitGrid chip rated for a given clock rate, it doesn't matter how you program it, because all logic is latched, the clock skew will always be within bounds. With an FPGA, you've got to run simulations, adjust timings, etc and wait for things to compile and optimize to fit the chip, this can sometimes take a day.

glitchc 2y ago
Latency is only part of the problem. Unmanaged clock skew leads to race conditions, dramatically impacting circuit behaviour and reliability. That's the reason the industry overwhelmingly uses synchronized circuit designs and clocks to trigger transitions.
simne 2y ago
The goal of an FPGA is to get cheap prototype and/or for applications which don't need large batches, enough to ASIC become cost effective. Low latency links are just byproduct, added to improve FPGA performance (which is definitely bad if compare to ASIC), you don't have to use them in your design. If you will make working FPGA prototype, it would be not hard to convert them to ASIC. Happy birthday!
simne 2y ago
BTW have you hear about asynchronous FPGA programming (and asynchronous HDL design)? It was very popular subject some years ago.