5 ms·

If you've read the article, and thought to yourself... I wonder what it was like back then, and if there might be some other direction it could have gone, oh bo

If you've read the article, and thought to yourself... I wonder what it was like back then, and if there might be some other direction it could have gone, oh boy do I have a story (and opportunity) for you! It's my birthday today(61)... I'm up early to get a tooth pulled, and I read this wonderful story, and all I have is a tangent I hope some of you think is interesting. It would be nice if someone who isn't brain-foggy could run with the idea and make the Billion dollars or so I think can be wrung out of it. You get a bowl of spaghetti, that could contain the key to Petaflops, secure computing, and a new universal solvent of computing like the Turing machine, as an instructional model. The BitGrid is an FPGA without all the fancy routing hardware, that being replace with a grid of latches... if fact, the whole chip would consist almost entirely of D flip-flops and 16:1 multiplexers. (I lack the funds to do a TinyTapeout, but started going there should the money appear) All the computation happens in cells that are 4 bit in, 4 bit out Look up tables. (Mostly so signals can cross without XOR tricks, etc) For the times you need a chunk of RAM, the closest I got is using one of the tables as a 16 bit wide shift register, which I've decided to call isolinear memory[6] You can try the online React emulator I'm still working on [1], and see the source[2]. Or the older one I wrote in Pascal, that's MUCH faster[3]. There's a writeup from someone else about it as an Esoteric Language[4]. I've even written a blog about it over the years.[5] It's all out in public, for decades up to the present... so it should be easy to contest any patents, and keep it fun. I'm sorry it's all a big incoherent mess.... completely replacing an architecture is freaking hard, especially when confronted with 79 years of optimization in another direction. I do think it's possible to target it with LLVM, if you're feeling frisky. [1] https://mikewarot.github.io/bitgrid-react-app/ https://mikewarot.github.io/bitgrid-react-app/ [2] https://github.com/mikewarot/bitgrid-react-app https://github.com/mikewarot/bitgrid-react-app [3] https://github.com/mikewarot/Bitgrid https://github.com/mikewarot/Bitgrid [4] https://esolangs.org/wiki/Bitgrid https://esolangs.org/wiki/Bitgrid [5] https://bitgrid.blogspot.com/ https://bitgrid.blogspot.com/ [6] https://bitgrid.blogspot.com/2024/09/bitgrid-and-isolinear-memory.html https://bitgrid.blogspot.com/2024/09/bitgrid-and-isolinear-m...

NetOpWibby 2y ago
Happy birthday! I have no idea what you’re talking about but I’m gonna follow these links.
gradschool 2y ago
I don't like to rain on anyone's parade, but this is at least the third time I've seen one of these comments, and if it were me I'd want someone to point out a drawback that these young whippersnappers might be too respectful to mention. Isn't it a truism in modern computer architecture that computation is cheap whereas communication is expensive? That "fancy routing hardware" is what mitigates this problem as far as possible by enabling signals to propagate between units in the same clock domain within a single clock period. Your system makes the problem worse by requiring a number of clock periods at best directly proportional to their physical separation, and worse depending on the layout. If I were trying to answer this criticism, I'd start by looking up systolic arrays (another great idea that never went anywhere) and finding out what applications were suited to them if any.
- kije 2y ago
  Not sure why you're saying that systolic arrays never went anywhere. They're widely used for matrix operations in many linear algebra accelerators and tensor units (yes, largely in research), but they are literally the core of Google's TPU [1] and AWS EC2 Inf1 instances [2]. [1] https://cloud.google.com/blog/products/ai-machine-learning/an-in-depth-look-at-googles-first-tensor-processing-unit-tpu https://cloud.google.com/blog/products/ai-machine-learning/a... [2] https://aws.amazon.com/blogs/aws/amazon-ecs-now-supports-ec2-inf1-instances/ https://aws.amazon.com/blogs/aws/amazon-ecs-now-supports-ec2...
glitchc 2y ago
Sorry to burst your bubble but modern FPGAs are already designed this way (latches paired with muxes and LUTs across the lattice). Take a look at the specs for a Xilinx Spartan variant. You still need the routing bits because clock skew and propagation delay are real problems in large circuits.
- mikewarot 2y ago
  Yes, I know about clock skew and FPGAs. They are an optimization for latency, which can be quite substantial and make/break applications. The goal of an FPGA is to get a signal through the chip in as few nanoSeconds as possible. It would be insane to rip out that hardware in that case. However.... I care about throughput, and latency usually doesn't matter much. In many cases, you could tolerate startup delays in the milliseconds. Because everything is latched, clock skew isn't really an issue. All of the lines carrying data are short, VERY short, thus lower capacitance. I believe it'll be possible to bring the clock rates up into the Gigahertz. I think it'll be possible to push 500 Mhz on the Skywater 130 process that Tiny Tapeout uses. (Not outside of the chip, of course, but internally) [edit/append] Once you've got a working BitGrid chip rated for a given clock rate, it doesn't matter how you program it, because all logic is latched, the clock skew will always be within bounds. With an FPGA, you've got to run simulations, adjust timings, etc and wait for things to compile and optimize to fit the chip, this can sometimes take a day.
  - glitchc 2y ago
    Latency is only part of the problem. Unmanaged clock skew leads to race conditions, dramatically impacting circuit behaviour and reliability. That's the reason the industry overwhelmingly uses synchronized circuit designs and clocks to trigger transitions.
  - simne 2y ago
    The goal of an FPGA is to get cheap prototype and/or for applications which don't need large batches, enough to ASIC become cost effective. Low latency links are just byproduct, added to improve FPGA performance (which is definitely bad if compare to ASIC), you don't have to use them in your design. If you will make working FPGA prototype, it would be not hard to convert them to ASIC. Happy birthday!
mikewarot 2y ago
Please also note that the ENIAC slowed down by a factor of 6 (according to Wikipedia) after it's conversion to von Neumanns architecture. BitGrid is slower than an FPGA, but far more flexible for general purpose computation.

NetOpWibby 2y ago

Happy birthday! I have no idea what you’re talking about but I’m gonna follow these links.

gradschool 2y ago

I don't like to rain on anyone's parade, but this is at least the third time I've seen one of these comments, and if it were me I'd want someone to point out a drawback that these young whippersnappers might be too respectful to mention. Isn't it a truism in modern computer architecture that computation is cheap whereas communication is expensive? That "fancy routing hardware" is what mitigates this problem as far as possible by enabling signals to propagate between units in the same clock domain within a single clock period. Your system makes the problem worse by requiring a number of clock periods at best directly proportional to their physical separation, and worse depending on the layout. If I were trying to answer this criticism, I'd start by looking up systolic arrays (another great idea that never went anywhere) and finding out what applications were suited to them if any.

kije 2y ago
Not sure why you're saying that systolic arrays never went anywhere. They're widely used for matrix operations in many linear algebra accelerators and tensor units (yes, largely in research), but they are literally the core of Google's TPU [1] and AWS EC2 Inf1 instances [2]. [1] https://cloud.google.com/blog/products/ai-machine-learning/an-in-depth-look-at-googles-first-tensor-processing-unit-tpu https://cloud.google.com/blog/products/ai-machine-learning/a... [2] https://aws.amazon.com/blogs/aws/amazon-ecs-now-supports-ec2-inf1-instances/ https://aws.amazon.com/blogs/aws/amazon-ecs-now-supports-ec2...

glitchc 2y ago

Sorry to burst your bubble but modern FPGAs are already designed this way (latches paired with muxes and LUTs across the lattice). Take a look at the specs for a Xilinx Spartan variant. You still need the routing bits because clock skew and propagation delay are real problems in large circuits.

mikewarot 2y ago
Yes, I know about clock skew and FPGAs. They are an optimization for latency, which can be quite substantial and make/break applications. The goal of an FPGA is to get a signal through the chip in as few nanoSeconds as possible. It would be insane to rip out that hardware in that case. However.... I care about throughput, and latency usually doesn't matter much. In many cases, you could tolerate startup delays in the milliseconds. Because everything is latched, clock skew isn't really an issue. All of the lines carrying data are short, VERY short, thus lower capacitance. I believe it'll be possible to bring the clock rates up into the Gigahertz. I think it'll be possible to push 500 Mhz on the Skywater 130 process that Tiny Tapeout uses. (Not outside of the chip, of course, but internally) [edit/append] Once you've got a working BitGrid chip rated for a given clock rate, it doesn't matter how you program it, because all logic is latched, the clock skew will always be within bounds. With an FPGA, you've got to run simulations, adjust timings, etc and wait for things to compile and optimize to fit the chip, this can sometimes take a day.
- glitchc 2y ago
  Latency is only part of the problem. Unmanaged clock skew leads to race conditions, dramatically impacting circuit behaviour and reliability. That's the reason the industry overwhelmingly uses synchronized circuit designs and clocks to trigger transitions.
- simne 2y ago
  The goal of an FPGA is to get cheap prototype and/or for applications which don't need large batches, enough to ASIC become cost effective. Low latency links are just byproduct, added to improve FPGA performance (which is definitely bad if compare to ASIC), you don't have to use them in your design. If you will make working FPGA prototype, it would be not hard to convert them to ASIC. Happy birthday!

mikewarot 2y ago

Please also note that the ENIAC slowed down by a factor of 6 (according to Wikipedia) after it's conversion to von Neumanns architecture. BitGrid is slower than an FPGA, but far more flexible for general purpose computation.