5 ms·

> 10^5 flip-flops is about 12.2KiB of memory It is reasonable amount for CISC CPU cache, as for CISC normal to have small number of registers (RISC is definite

by simne 2y ago

> 10^5 flip-flops is about 12.2KiB of memory It is reasonable amount for CISC CPU cache, as for CISC normal to have small number of registers (RISC is definitely multiple-register machine, as memory operations are expensive with RISC paradigm).

Someone 2y ago
I don’t think that’s correct. Ideally, your working set fits into the cache, and that doesn’t get smaller or larger when you use a RISC CPU. (There may be an effect because of instruction density, but that’s not very big, and will have less of an effect the larger your working set)
- simne 2y ago
  > Ideally, your working set fits into the cache Ideally, your working set fits into the registers, and that was most win feature or RISC, having relatively simple hardware (if compared to genuine CISC, like IBM-360 mainframes) they saved significant space on chip for more registers. - Register-register operations are definitely avoid memory wall, so data cache become insignificant. Sure, if we compare comparable, not apples vs carrots.
  - simne 2y ago
    If you are unlucky, so your working set don't fit into the registers, in this case you sure will deal with memory bus and with cache hierarchy. But best if you just don't touch memory at all, making all processing in your code in registers.
Joker_vD 2y ago
> for CISC normal to have small number of registers A very common fallacy. For CISC it's normal to have small number of programmer-visible (architectural) registers. But nothing stops them from having large register files having about a hundred or two of physical registers which are renamed during the execution. IBM has been doing this sort of thing since the late sixties. Modern x64 have IIRC 180 integer general-purpose registers, and I imagine this number can be increased further: say, AMD's Am29000 from 1985 had 192 registers... and honestly, having more than 16 programmer-visible registers is not that useful when 99.999% of the code is written for the high-level languages with separate-compilation schemes: any function call requires you to spill all your live data from the registers to the memory; having call-preserved registers means that you can do such a spill only once, at the start of the outer function, but it still has to happen. And outside of the function calls, in the real world programs most of the expressions that use only built-in operators either don't require more than 4 registers calculate, or can be done much more efficiently using vector/SIMD instructions and registers anyway.
- simne 2y ago
  > For CISC it's normal to have small number of programmer-visible (architectural) registers You compare apples with carrots. Question is what you name CISC/RISC. If under CISC considered early single-chip stubs like 8080 or even x86 before AMD64, this is one history, but if CISC are IBM/360,/370,/390 and DEC PDP-11 or later, this is totally other drama. Same is with RISC. What really important, genuine CISC typically have human-friendly instruction set, and even /360 assembler is comparable to C language; many RISCs are load/store architectures, don't have rich memory addressing modes, so by definition tied to work inside registers. Also, when compare similar level of manufacture and similar timeline, will easy see, 68k series have just 8 registers, but same era RISCs have at least 16.
  - Joker_vD 2y ago
    > You compare apples with carrots This analogy, I swear. Yes, I do, and this is an entirely reasonable comparison. Both are foodstuffs, and you can make pies out of both. But which pie would be healthier, and/or more nutritious? Now take the relative prices (or comparative difficulty of growing your own) of the ingredients into the account. > 68k series have just 8 registers Didn't they have 16?
    - simne 2y ago
      68k claimed to be 32-bit CPU, so it have 8 32-bit registers. Compare it with 16-bit CPU is just apples vs carrots.
      - Joker_vD 2y ago
        68000 had sixteen 32-bit registers, but no 32-bit ALUs; it used 3 16-bit ALUs instead. This has been rectified in 68020 which had fully 32-bit ALU. And Western Electric 32000, a CISC processor from the same period, also had 16 32-bit registers.
        simne 2y ago
        > 68000 had sixteen 32-bit registers It is your own opinion. Wikipedia have other definition.

by simne 2y ago

Someone 2y ago

I don’t think that’s correct. Ideally, your working set fits into the cache, and that doesn’t get smaller or larger when you use a RISC CPU. (There may be an effect because of instruction density, but that’s not very big, and will have less of an effect the larger your working set)

simne 2y ago
> Ideally, your working set fits into the cache Ideally, your working set fits into the registers, and that was most win feature or RISC, having relatively simple hardware (if compared to genuine CISC, like IBM-360 mainframes) they saved significant space on chip for more registers. - Register-register operations are definitely avoid memory wall, so data cache become insignificant. Sure, if we compare comparable, not apples vs carrots.
- simne 2y ago
  If you are unlucky, so your working set don't fit into the registers, in this case you sure will deal with memory bus and with cache hierarchy. But best if you just don't touch memory at all, making all processing in your code in registers.

Joker_vD 2y ago

> for CISC normal to have small number of registers A very common fallacy. For CISC it's normal to have small number of programmer-visible (architectural) registers. But nothing stops them from having large register files having about a hundred or two of physical registers which are renamed during the execution. IBM has been doing this sort of thing since the late sixties. Modern x64 have IIRC 180 integer general-purpose registers, and I imagine this number can be increased further: say, AMD's Am29000 from 1985 had 192 registers... and honestly, having more than 16 programmer-visible registers is not that useful when 99.999% of the code is written for the high-level languages with separate-compilation schemes: any function call requires you to spill all your live data from the registers to the memory; having call-preserved registers means that you can do such a spill only once, at the start of the outer function, but it still has to happen. And outside of the function calls, in the real world programs most of the expressions that use only built-in operators either don't require more than 4 registers calculate, or can be done much more efficiently using vector/SIMD instructions and registers anyway.

simne 2y ago
> For CISC it's normal to have small number of programmer-visible (architectural) registers You compare apples with carrots. Question is what you name CISC/RISC. If under CISC considered early single-chip stubs like 8080 or even x86 before AMD64, this is one history, but if CISC are IBM/360,/370,/390 and DEC PDP-11 or later, this is totally other drama. Same is with RISC. What really important, genuine CISC typically have human-friendly instruction set, and even /360 assembler is comparable to C language; many RISCs are load/store architectures, don't have rich memory addressing modes, so by definition tied to work inside registers. Also, when compare similar level of manufacture and similar timeline, will easy see, 68k series have just 8 registers, but same era RISCs have at least 16.
- Joker_vD 2y ago
  > You compare apples with carrots This analogy, I swear. Yes, I do, and this is an entirely reasonable comparison. Both are foodstuffs, and you can make pies out of both. But which pie would be healthier, and/or more nutritious? Now take the relative prices (or comparative difficulty of growing your own) of the ingredients into the account. > 68k series have just 8 registers Didn't they have 16?
  - simne 2y ago
    68k claimed to be 32-bit CPU, so it have 8 32-bit registers. Compare it with 16-bit CPU is just apples vs carrots.
    - Joker_vD 2y ago
      68000 had sixteen 32-bit registers, but no 32-bit ALUs; it used 3 16-bit ALUs instead. This has been rectified in 68020 which had fully 32-bit ALU. And Western Electric 32000, a CISC processor from the same period, also had 16 32-bit registers.
      - simne 2y ago
        > 68000 had sixteen 32-bit registers It is your own opinion. Wikipedia have other definition.