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I'm not a HW guy but my HW friends have been designing HCI solutions with AMD for maximum IO throughput because AMD CPUs have more PCI lanes.
by INTPenis 2y ago
I'm not a HW guy but my HW friends have been designing HCI solutions with AMD for maximum IO throughput because AMD CPUs have more PCI lanes.
- storrgie 2y agoI think for _most_ people it comes down to this: how much can I cram into the platform. More lanes is more high speed storage, special purpose processing, and networking interfaces.
- wmf 2y agoVMware users are starting to say that Epyc is too powerful for one server because they don't want to lose too much capacity due to a single server failure. Tangentially related, network switch ASICs also have too much capacity for a single rack.