5 ms·
I assume the driving of choosing low er level architectures over this sort of "smart" CPU was the overall complexity of the chip, but since the 80' with been pi
by tc4v 2y ago
I assume the driving of choosing low er level architectures over this sort of "smart" CPU was the overall complexity of the chip, but since the 80' with been piling so much abstraction and complexity that there is nithing "vanilla" in modern CPU. I wonder if such "higher level" CPUs could be interesting implented on top of the usual microcode architecture. They would for example give more information to the branch predictor, which could have a positive impact.
- surfingdino 2y agoWasn't RISC an attempt at addressing that growing abstraction and complexity?
- dbspin 2y agoDefinitely, some great interviews out there with Sophie Wilson (co-creator of ARM) discussing how supporting arbitrary languages was a goal of the ARM project (based on the Berkeley RISC research) from the beginning. 1 -https://youtu.be/jhwwrSaHdh8?si=mj1vl_Wy0MF-IQL4 https://youtu.be/jhwwrSaHdh8?si=mj1vl_Wy0MF-IQL4 2 - https://youtu.be/IASlQ9kjRRA?si=OPA1atrtlLdXEfTo https://youtu.be/IASlQ9kjRRA?si=OPA1atrtlLdXEfTo
- pinewurst 2y agoIt wasn’t a single or even custom chip though - built from standard bitslice.