2 ms·
When compiling for e.g. ARM, however, the two shifts tends to be compiled into a single bitfield-extract instruction. RISC-V doesn't have such an instruction b
by Findecanor 2y ago
When compiling for e.g. ARM, however, the two shifts tends to be compiled into a single bitfield-extract instruction.
RISC-V doesn't have such an instruction but there are cores that do macro-op fusion of just that sequence.