3 ms·
That neatly lines up with their actual GPU cores which are also 1024 bits wide (32 lanes of FP32) but I have no idea why they would need to go that wide in an a
by jsheard 2y ago
That neatly lines up with their actual GPU cores which are also 1024 bits wide (32 lanes of FP32) but I have no idea why they would need to go that wide in an auxiliary management core.
- camel-cdr 2y agoI noticed that as well, but it's still not obvious to me why, they must do a decent amount of complex computation on them. Otherwise, they could've also used VLEN=128 with LMUL=8 to get effectively four 1024-bit vector registers.