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What really surprised me to learn is that use some VLEN=1024 RVV 1.0 cores: https://x.com/FlorianWoh/status/1848771326791848438/photo/3 https://x.com/FlorianWoh
by camel-cdr 2y ago
What really surprised me to learn is that use some VLEN=1024 RVV 1.0 cores: https://x.com/FlorianWoh/status/1848771326791848438/photo/3 https://x.com/FlorianWoh/status/1848771326791848438/photo/3
- jsheard 2y agoThat neatly lines up with their actual GPU cores which are also 1024 bits wide (32 lanes of FP32) but I have no idea why they would need to go that wide in an auxiliary management core.
- camel-cdr 2y agoI noticed that as well, but it's still not obvious to me why, they must do a decent amount of complex computation on them. Otherwise, they could've also used VLEN=128 with LMUL=8 to get effectively four 1024-bit vector registers.