3 ms·

Maybe for variable variable-length shifts but for constant variable-length shifts, SHL reg, imm8 is single cycle on recent x86_64 microarchitectures.

• Sesse__ 2y ago
  But xor and sub can go in way more ports, giving you higher throughput.
  • dzaima 2y ago
    "way more" is 2 vs 4 ports (→5 for ≥alderlake); 1/cycle via shifts is probably good enough for most use-cases (though perhaps the more focused port pressure could be an issue with larger context). And with hard-coded immediates xor+sub also ends up at twice the code size as shl+shr, so there's some trade-off. (but yeah if code size isn't a concern, xor+sub wins out)
    • Sesse__ 2y ago
      Twice or more is pretty significant, wouldn't you say? :-) Code size is a valid concern, though.
  • Findecanor 2y ago
    When compiling for e.g. ARM, however, the two shifts tends to be compiled into a single bitfield-extract instruction. RISC-V doesn't have such an instruction but there are cores that do macro-op fusion of just that sequence.