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> Through years of architectural improvements and ecosystem development, ARM gradually expanded into mobile devices, then servers, and now even high-performance

> Through years of architectural improvements and ecosystem development, ARM gradually expanded into mobile devices, then servers, and now even high-performance desktop systems Also, a complete re-boot of the ISA with AArch64. This is a mostly-uninformed theory, but I'd love to hear thoughts on it: AArch64 was a substantial break from AArch32, with lots of design changes intended to ease superscalar OoO implementations. Conditional execution mostly gone, Thumb gone, PC no longer a GPR, etc. Clearly, AArch64 has excelled for this. There are even rumors that Apple basically commissioned AArch64 for the types of cores they wanted to build: https://news.ycombinator.com/item?id=31368489 https://news.ycombinator.com/item?id=31368489 RISC-V is quite similar to MIPS, an ISA which hasn't had a high-performance leading-edge implementation in 20+ years (dating back to SGI's last parts). Will this heritage make it harder to build high-performance OoO implementations? Does RISC-V need an AArch64-style reboot? Maybe this can be mostly done through extensions?

bhouston 2y ago
That is a really good question. I wish we had Jim Kelly here to answer that. :)
- tromp 2y ago
  Or Jim Keller even:-)
panick21_ 2y ago
The people who did RISC-V knew about AArch64 and designed it with hit performance in mind. Almost no conditional execution, a compressed mode that does cause issues and actually improves performance, no branch delay slot, no condition codes, no register windows and so on. They have a whole book where they go threw each instruction and explain why they added it. Its not perfectly optimized only for high performance, but that was certainty a major factor. The architecture has been evaluated by people like Dave Ditzel and Jim Keller. The leader designer for Jim Kellers company worked on the M1. And they all seem to think that its a good design.

bhouston 2y ago

That is a really good question. I wish we had Jim Kelly here to answer that. :)

tromp 2y ago
Or Jim Keller even:-)

panick21_ 2y ago

The people who did RISC-V knew about AArch64 and designed it with hit performance in mind. Almost no conditional execution, a compressed mode that does cause issues and actually improves performance, no branch delay slot, no condition codes, no register windows and so on. They have a whole book where they go threw each instruction and explain why they added it. Its not perfectly optimized only for high performance, but that was certainty a major factor. The architecture has been evaluated by people like Dave Ditzel and Jim Keller. The leader designer for Jim Kellers company worked on the M1. And they all seem to think that its a good design.