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The article addresses this question: "RISC-V implementations in the wild lack advanced features that modern CPUs rely on for speed, including sophisticated pip

The article addresses this question: "RISC-V implementations in the wild lack advanced features that modern CPUs rely on for speed, including sophisticated pipelining mechanisms, out-of-order execution capabilities, advanced branch prediction, and multi-tiered cache hierarchies. Most commercial RISC-V chips remain in-order processors, meaning they execute instructions sequentially rather than optimizing their order for performance. This architectural simplicity creates a fundamental performance ceiling that's difficult to overcome without significant architectural changes."

rwmj 2y ago
This ignores two major server vendors, Rivos & Ventana (three if you include Qualcomm) who do have all those features.
- bhouston 2y ago
  I am excited to see innovation come in this area. I wasn't saying that there won't be improvements or more innovation, just that the currently released chips are not performant.
- Rochus 2y ago
  Are they included in https://browser.geekbench.com/search?q=RISC-V https://browser.geekbench.com/search?q=RISC-V? I dind't get any hits when searching e.g. for Rivos.
- arp242 2y ago
  As I understand it, Rivos hasn't actually shipped anything; from https://www.rivosinc.com/technology https://www.rivosinc.com/technology: "Rivos has not yet revealed details of its products or technology publicly." Great that they're working on that, but when discussing the _current_ state of the RISC-V ecosystem, I think they can be safely ignored until such a time that they actually start shipping stuff. It seems Ventana has shipped the Veyron V1, but I'm having a hard time finding concrete information on that in a quick search (other than from Ventana themselves), so not entirely sure what the status of that is? Their V2 chip is planned for 2025.
jauntywundrkind 2y ago
But these aren't Instruction Set Architecture (IS details. As mentioned in article, Berkeley's SonicBOOM is out of order. And you could certainly enhance the memory architecture with multi-level caches easily; the ISA is blind to this (consider how little x86 ISA has improved to tackle ever improving cache/memory strategies since i386). RISC-V is also extensible. So you can keep improving things! The incredibly awesome efficiency-foxused PULP group is working on a massive many-core research chip Occamy. It has huge vector processing units, many many many of them. Ok, so, promising. https://pulp-platform.org/occamy/ https://pulp-platform.org/occamy/ And they have their own extension, Semantic Streaming Registers, which add a very CISC-y set of instructions that combine real work and load/store (and incrementing the data pointer for the next loop), allowing DSP like performance in loops. Super super slick extension to massively increase the throughput, improve the ISA & reduce it's footprint in loops. https://arxiv.org/abs/1911.08356 https://arxiv.org/abs/1911.08356
bee_rider 2y ago
That’s an odd match to the title. Who is thinking about RISC-V in 2024 without knowing that those features are typically missing? It is early days.

rwmj 2y ago

This ignores two major server vendors, Rivos & Ventana (three if you include Qualcomm) who do have all those features.

bhouston 2y ago
I am excited to see innovation come in this area. I wasn't saying that there won't be improvements or more innovation, just that the currently released chips are not performant.
Rochus 2y ago
Are they included in https://browser.geekbench.com/search?q=RISC-V https://browser.geekbench.com/search?q=RISC-V? I dind't get any hits when searching e.g. for Rivos.
arp242 2y ago
As I understand it, Rivos hasn't actually shipped anything; from https://www.rivosinc.com/technology https://www.rivosinc.com/technology: "Rivos has not yet revealed details of its products or technology publicly." Great that they're working on that, but when discussing the _current_ state of the RISC-V ecosystem, I think they can be safely ignored until such a time that they actually start shipping stuff. It seems Ventana has shipped the Veyron V1, but I'm having a hard time finding concrete information on that in a quick search (other than from Ventana themselves), so not entirely sure what the status of that is? Their V2 chip is planned for 2025.

jauntywundrkind 2y ago

But these aren't Instruction Set Architecture (IS details. As mentioned in article, Berkeley's SonicBOOM is out of order. And you could certainly enhance the memory architecture with multi-level caches easily; the ISA is blind to this (consider how little x86 ISA has improved to tackle ever improving cache/memory strategies since i386). RISC-V is also extensible. So you can keep improving things! The incredibly awesome efficiency-foxused PULP group is working on a massive many-core research chip Occamy. It has huge vector processing units, many many many of them. Ok, so, promising. https://pulp-platform.org/occamy/ https://pulp-platform.org/occamy/ And they have their own extension, Semantic Streaming Registers, which add a very CISC-y set of instructions that combine real work and load/store (and incrementing the data pointer for the next loop), allowing DSP like performance in loops. Super super slick extension to massively increase the throughput, improve the ISA & reduce it's footprint in loops. https://arxiv.org/abs/1911.08356 https://arxiv.org/abs/1911.08356

bee_rider 2y ago

That’s an odd match to the title. Who is thinking about RISC-V in 2024 without knowing that those features are typically missing? It is early days.