3 ms·
Isn't the problem the lack of advanced features for executing the current ISA with speed? I thought RISC-V chips seen in the wild do not pipelining, out-of-ord
by bhouston 2y ago
Isn't the problem the lack of advanced features for executing the current ISA with speed? I thought RISC-V chips seen in the wild do not pipelining, out-of-order, register renaming, multiple int/float/logic units, speculation, branch predictors, multi-tier caching, etc. The lack of speed isn't really related to a few missing vector instructions.
- monocasa 2y agoThere's a lot of cores that do all of that. Most cores are pipelined; it is RISC after all. There are quite a few superscalar cores, even a c906 is superscalar. The c910/c920 is an OoO, renaming core, with speculation. What they're lacking is area and power. A ROB with six entries is not going to compete with a ROB of six hundred entries.