3 ms·
It is much more than just SIMD. I think RISC-V chips in the wild do not do things like pipelining, out-of-order, register renaming, multiple int/float/logic un
by bhouston 2y ago
It is much more than just SIMD.
I think RISC-V chips in the wild do not do things like pipelining, out-of-order, register renaming, multiple int/float/logic units, speculation, branch predictors, smart caching.
I think all existing RISC-V chips in the wild right now are just simplistic in-order processors.
- avvvv 2y agoCould patents be one of the reason why? Genuine question.
- shash 2y agoAlmost all in-order processors will do pipelining, so that's there. Many are even multi-issue. Andes has an out of order core [1] and so does SiFive (though I don't know of many actual chips using these. [1] https://www.andestech.com/en/2024/01/05/andes-announces-general-availability-of-the-new-risc-v-out-of-order-superscalar-multicore-processor-the-andescore-ax65/ https://www.andestech.com/en/2024/01/05/andes-announces-gene... [2] https://www.sifive.com/cores/performance-p650-670 https://www.sifive.com/cores/performance-p650-670
- hajile 2y agoYou are wildly mistaken here. Back in 2016, BOOMv1 (Berkley Out-of-Order Machine) had pipelining, register renaming, 3-wide dispatch, branch predictor, caches, etc. A quick google seems to indicate that it was started in 2011 and had taped out 11 times by 2016 (with actual production apparently being done on IBM 45nm). They are on BOOMv3 now.