4 ms·
Years ago. DRAM uses a capacitor. Those capacitors essentially hit a hard limit at around 400MHz for our traditional materials a very long time ago. This means
by hajile 2y ago
Years ago.
DRAM uses a capacitor. Those capacitors essentially hit a hard limit at around 400MHz for our traditional materials a very long time ago. This means that if you need to sequentially read random locations from RAM, you can't do it faster than 400MHz. Our only answer here is better AI prefetchers and less-random memory patterns in our software (the penalty for not prefetching is so great that theoretically less efficient algorithms can suddenly become more efficient if they are simply more predictable).
As to capacitor sizes, we've been at the volume limit for quite a while. When the capacitor is discharged, we must amplify the charge. That gets harder as the charge gets weaker and there's a fundamental limit to how small you can go. Right now, each capacitor has somewhere in the range of a mere 40,000 electrons holding the charge. Going lower dramatically increases the complexity of trying to tell the signal from the noise and dealing with ever-increasing quantum effects.
Getting more capacitors closer means a smaller diameter, but keeping the same volume means making the cylinder longer. You quickly reach a point where even dramatic increases in height (something very complicated to do in silicon) give only minuscule decreases in diameter.
- aidenn0 2y agoIf that's the case, why haven't we switched to SRAM? Isn't it only about 4x the price at any given process node?
- RF_Savage 2y agoThat 4x the price does also explain why it has not happened.
- guerrilla 2y agoYeah but why don't we have like 500MB of SRAM per 8GB of RAM. Certain addresses could be faster, in the same way /dev/shm/ is faster.
- turtles3 2y agoThis is sort of the role that L3 cache plays already. Your proposal would be effectively an upgradable L4 cache. No idea if the economics on that are worth it vs bigger DRAM so you have less pressure on the nvme disk.
- guerrilla 2y agoCache is not general purpose as far as I know. I want to be able to do whatever I want with it.
- MichaelZuo 2y agoWhere’s the market demand for that?
- ghaff 2y agoYeah, you’re basically betting that people will put a lot of effort in trying to out/optimize the hardware and perhaps to some degree the OS. Not a good bet. When SMP first came out we had one large customer that wanted to manually handle scheduling themselves. That didn’t last long.
- guerrilla 2y agoEffort? It's not like it's hard to map an SRAM chip to whatever address you want and expose it raw or as a block device. That's a 100 LOC kernel module.
- guerrilla 2y agoWhere is the market demand for faster RAM? This isn't a good question.
- MichaelZuo 2y agoGamers, 3D modelling professionals, IBM, HP, ORACLE, many IT departments, etc… ?
- aidenn0 2y agoIf it were even 20% faster than DRAM, there would be a market for it at the higher price. The post I replied to was asserting that there was a physical limit of 400MHz for DRAM entirely due to the capacitor. If SRAM could run with lower latency, memory-bound workloads would get comparably faster.
- kstrauser 2y agoWhat does “faster than 400MHz” mean in this context? Does that mean you can’t ask for a unit of memory from it more than 400M times a second? If so, what’s the basic unit there, a bit? A word? I built a little CPU in undergrad but never got around to building RAM and admit it’s still kind of a black box to me. Bonus question: When I had an Amiga, we’d buy 50 or 60ns RAM. Any idea what that number meant, or what today’s equivalent would be?
- hajile 2y agoThe capacitors take time to charge and discharge. You can't do that more than around 400MHz with current materials. You are correct that it means you can't access the same bit of memory more than 400M/sec. This is the same whether you are accessing 1bit or 1M bits because the individual capacitors that make up those bits can't be charged/discharged any faster. When we moved from SDR to DDR1, latencies dropped from 20-25ns to about 15ns too, but if you run the math, we've been at 13-17ns of latency ever since.
- rasz 2y agoYep, we pretty much hit a wall during DDR2 rein https://en.wikipedia.org/wiki/CAS_latency#Memory_timing_examples https://en.wikipedia.org/wiki/CAS_latency#Memory_timing_exam...
- anticensor 2y agoNo, 7.5 to 9.75ns during the DDR4 rein (DDR4-4266), according to that page.
- rasz 2y agoDDR2-1066 CL4 is also 7.5ns to first data.
- anticensor 2y agoBut DDR2-1066 is worse in second and later accesses.