5 ms·

We're not quite there yet. A bunch of mission critical stuff like SIMD were only added in the last 2-3 years. As it takes 4-5 years to design/ship high-performa

by hajile 2y ago

We're not quite there yet. A bunch of mission critical stuff like SIMD were only added in the last 2-3 years. As it takes 4-5 years to design/ship high-performance chips, we still have a ways to go. Ventana Veyron looks interesting. Tenstorrent's upcoming 8-wide design should perform well. Qualcomm pitched making a bunch of changes to RISC-V that would move it closer to ARM64 and make porting easier, so I think it's an understatement to say that they are considering the idea. If ISA doesn't matter, why pay tons of money for the ISA?

bhouston 2y ago
It is much more than just SIMD. I think RISC-V chips in the wild do not do things like pipelining, out-of-order, register renaming, multiple int/float/logic units, speculation, branch predictors, smart caching. I think all existing RISC-V chips in the wild right now are just simplistic in-order processors.
- avvvv 2y ago
  Could patents be one of the reason why? Genuine question.
- shash 2y ago
  Almost all in-order processors will do pipelining, so that's there. Many are even multi-issue. Andes has an out of order core [1] and so does SiFive (though I don't know of many actual chips using these. [1] https://www.andestech.com/en/2024/01/05/andes-announces-general-availability-of-the-new-risc-v-out-of-order-superscalar-multicore-processor-the-andescore-ax65/ https://www.andestech.com/en/2024/01/05/andes-announces-gene... [2] https://www.sifive.com/cores/performance-p650-670 https://www.sifive.com/cores/performance-p650-670
- hajile 2y ago
  You are wildly mistaken here. Back in 2016, BOOMv1 (Berkley Out-of-Order Machine) had pipelining, register renaming, 3-wide dispatch, branch predictor, caches, etc. A quick google seems to indicate that it was started in 2011 and had taped out 11 times by 2016 (with actual production apparently being done on IBM 45nm). They are on BOOMv3 now.
shash 2y ago
There were two competing SIMD specs, and personally I'm glad that RVV won out over PSIMD. It's an easier programmer's view and fewer instructions to implement.
- snvzz 2y ago
  RVV was not going to lose this one. RVV's roots run deeper than RISC-V's. RISC-V was created because UC Berkeley's vector processor needed a scalar ISA, and the incumbents were not suitable. Then, it uncovered pre-existing interest in open ISAs, as companies started showing up with the desire for a frozen spec. Legend is that MIPS quoted UC Berkeley some silly amount. We can thank them for RISC-V. Ironically, they ended up embracing RISC-V as well.

by hajile 2y ago

bhouston 2y ago

It is much more than just SIMD. I think RISC-V chips in the wild do not do things like pipelining, out-of-order, register renaming, multiple int/float/logic units, speculation, branch predictors, smart caching. I think all existing RISC-V chips in the wild right now are just simplistic in-order processors.

avvvv 2y ago
Could patents be one of the reason why? Genuine question.
shash 2y ago
Almost all in-order processors will do pipelining, so that's there. Many are even multi-issue. Andes has an out of order core [1] and so does SiFive (though I don't know of many actual chips using these. [1] https://www.andestech.com/en/2024/01/05/andes-announces-general-availability-of-the-new-risc-v-out-of-order-superscalar-multicore-processor-the-andescore-ax65/ https://www.andestech.com/en/2024/01/05/andes-announces-gene... [2] https://www.sifive.com/cores/performance-p650-670 https://www.sifive.com/cores/performance-p650-670
hajile 2y ago
You are wildly mistaken here. Back in 2016, BOOMv1 (Berkley Out-of-Order Machine) had pipelining, register renaming, 3-wide dispatch, branch predictor, caches, etc. A quick google seems to indicate that it was started in 2011 and had taped out 11 times by 2016 (with actual production apparently being done on IBM 45nm). They are on BOOMv3 now.

shash 2y ago

There were two competing SIMD specs, and personally I'm glad that RVV won out over PSIMD. It's an easier programmer's view and fewer instructions to implement.

snvzz 2y ago
RVV was not going to lose this one. RVV's roots run deeper than RISC-V's. RISC-V was created because UC Berkeley's vector processor needed a scalar ISA, and the incumbents were not suitable. Then, it uncovered pre-existing interest in open ISAs, as companies started showing up with the desire for a frozen spec. Legend is that MIPS quoted UC Berkeley some silly amount. We can thank them for RISC-V. Ironically, they ended up embracing RISC-V as well.