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>Since the i80486 has no management engine, running an open source BIOS would make it fully, 100% open. Note there are fully open source RISC-V designs you can
by snvzz 2y ago
>Since the i80486 has no management engine, running an open source BIOS would make it fully, 100% open.
Note there are fully open source RISC-V designs you can program into a FPGA that will yield higher performance than any 486 by orders of magnitude.
- transpute 2y agoWhat's an example FPGA for this purpose?
- buildbot 2y agoThis is one that you can use a fully open toolchain to build with: https://groupgets.com/products/orange-crab-85f-lattice-ecp5-fpga-development-kit?variant=39888044818617 https://groupgets.com/products/orange-crab-85f-lattice-ecp5-... Which you can build a RISCV core + linux for using: https://github.com/litex-hub/linux-on-litex-vexriscv https://github.com/litex-hub/linux-on-litex-vexriscv
- exe34 2y agoGoodness, this is cool! Do you have experience with this FPGA/toolchain? How long does it typically take to render something from Verilog to bitstream? E.g. a hello world adder v/s a risc v cpu?
- buildbot 2y agoI do! I’ve played around with it with this exact setup. It really depends on your processor, these toolchains really love a good mix of both high frequency and multi core. A hello world adder is less than a minute, a riscv core much much longer. A 16 core zen4/zen5 can compile the riscv core and linux in roughly 20 minutes? Compared to about an hour on a M1 Max macbook pro - It’s been awhile so I could be misremembering.
- deleted 2y ago[deleted]