As an FPGA developer: much agreed. We know exactly what's happening every clock cycle (or at least can), and often are able to have extremely deterministic comp

As an FPGA developer: much agreed. We know exactly what's happening every clock cycle (or at least can), and often are able to have extremely deterministic computation. You can do this on micros, but anything with good performance will have some caching, maybe context switching, etc. The polarfire SoC marketing has a graph showing either determinism or performance (I can dig it up if interested). In FPGA land, we define the pipelining such that we get both. I usually go out to an RFIC then stop caring, but you can calculate the latencies the as well.