Phoronix has a specific benchmark subset that tries to tease out (at least for zen5) a hint of how much the wider data-path matters vs. how much the frontend/IS

Phoronix has a specific benchmark subset that tries to tease out (at least for zen5) a hint of how much the wider data-path matters vs. how much the frontend/ISA extension itself, by disabling those selectively on an epyc zen5 chip: https://www.phoronix.com/review/amd-epyc-9755-avx512 https://www.phoronix.com/review/amd-epyc-9755-avx512 It's pretty clear that the ISA/frontend is much more impactful than the data-width on this set of workloads, and that also seems to jive with more indirect evidence from performance patterns more broadly. i.e. it's the new instructions (and potentially register width) that matter significantly more than the actually wider data-path.